• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.657-660
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• 2002

In this paper, the FFT processor for power measurement using VHDL (Very high-speed integrated circuit Hardware Description Language) is discussed. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the Input signal. The proposed system is based on FFT Processor which is designed using VHDL. In the design of FFT processor, $radix-2^2$ is adopted to reduce several complex multipliers for twiddle factor. And this processor adopt pipeline structure. Therefore, the system Is able to have both high hardware efficiency and high performance.

• 디지털산업정보학회논문지
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• 제12권4호
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2002년도 금형가공 심포지엄
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• pp.3-10
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• 2002

In this study on machine measuring system based on solid feature was developed. This system was applied with injection mold using 3 dimensional solid modeler for verification. Developed program include pre-processor, main processor, and post processor. In pre-processor there are functions which check intersection, simulate motion of probe and calculate measuring time. Main processor generates measuring path and output NC code in Unigraphics. In post-processor functions that include evaluation of undercut or overcut and display of measuring procedure are offered. In addition analysis module for quality control of measured data on manufactured product was developed with geometric and dimensional tolerance concept. As the result developed program could get stability of system, precision of product, rapidity and cost down of manufacturing process compared with before measuring process.

• 대한전자공학회논문지
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• 제22권5호
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• pp.39-44
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• 1985

본 논문에서는 공장 자동화 분야에 견합한 컴퓨터 시스템에 관하여 연구하였구 기초적인 satellite pro-cessor 시스템을 구성하였다. 전체 시스템은 하나의 운영체제에 의하여 제어되어 계층적 구조를 가진다. 기존의 UN상 시스템과 완전 호환성을 가지도록 하기 위하여 UNIX 운영체제를 수정 보완한 SPUNIX 운영체제를 구성하였다. 또한 응용 동작에 근접하는 동작을 하게 하기 위하여 특별한 프로그램 이것을 co-process라 부르기로 한다-과 이 co-process와 상호 협력하여 전체 동작을 형성하는 satellite pro-cessor kernel 등이 구성되었다. 많은 수의 satellite Processor가 대재하기 때문에 신뢰도, 확장성, 동시성(concurrence) 등의 특성이 나타난다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.664-665
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• 2013

본 논문에서는 멀티미디어프로세서 구성의 한가지 방법을 제안하였다. 제안한 멀티미디어프로세서는 각각의 문자, 소리, 비디오를 한 개의 칩안에서 다룰 수 있으며, 멀티미디어의 특징인 인터렉티브의 기능을 갖고 있다. 특히 제안한 멀티미디어프로세서는 소프트웨어 없이도 메모리매상의 어드레싱이 가능하다. 제아난 멀티미디어프로세서는 가상현실에 적용이 가능하다.

• 전자통신동향분석
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• 제32권6호
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• pp.57-65
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• 2017

Neural network based AI computing is a promising technology that reflects the recognition and decision operation of human beings. Early AI computing processors were composed of GPUs and CPUs; however, the dramatic increment of a floating point operation requires an energy efficient AI processor with a highly parallelized architecture. In this paper, we analyze the trends in processor architectures for AI computing. Some architectures are still composed using GPUs. However, they reduce the size of each processing unit by allowing a half precision operation, and raise the processing unit density. Other architectures concentrate on matrix multiplication, and require the construction of dedicated hardware for a fast vector operation. Finally, we propose our own inAB processor architecture and introduce domestic cutting-edge processor design capabilities.

• 한국정보전자통신기술학회논문지
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• 제2권3호
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• 한국정보과학회논문지:소프트웨어및응용
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• 제31권2호
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• pp.224-234
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• 2004

XML 문서 처리기는 XML 문서를 문서의 목적과 의미에 맞게 처리할 수 있어야 한다. XML의 DTD는 문서의 구조적인 정보만 제공하고 의미 정보는 제공하지 않기 때문에 문서 처리기를 자동적으로 생성하기 어렵다. 본 논문에서는 객체지향 속성 문법을 이용해서 XML 문서의 의미 정보를 기술하는 방법과 XML 문서 처리기를 자동적으로 생성할 수 있는 생성기를 소개한다. 문서 처리기 생성기는 문서처리기를 작성해야 하는 개발자의 시간과 노력을 감소시켜줄 것이다.

• 대한전자공학회논문지
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• 제23권6호
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• pp.902-907
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• 1986

A real-time microprogrammable digital signal processor is designed and implemented using the bit-slice logic, a parallel multiplier, 74 series TTLs and MOS memories. A microinstruction set for the processor is defined and an application program development system is constructed. For its performance evalution, a digital filter and FFT are implemented with this digital signal processor. It is proved that this processor is faster than commrcially available single chip digital signal processors such as \ulcornerD 7720, AMI 2811, enabling very high speed digital signal processing.