• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.427-437
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• 1994

Optimal static load balancing in star network configurations is considered. Three kinds of load balancing direction strategies are considered. First, a job arriving at the peripheral nodes may be processed either where it arrived(origin node) or transferred directly to central node Second, a job arriving at the central node may be processed there, or transferred to lightly loaded peripheral nodes. A nonlinear optimization problem is formulated. Using the optimal solution, an optimal load balancing algorithm is derived for the second load balancing strategy. Third a job arriving at the central node or a peripheral node may be processed either at origin node or transferred to another lightly loaded node (central or peripheral). A load balancing algorithm is derived for the third load balancing strategy. The effects of these three load balancing strategies are compared by numerical experiments. During the conduct of these in numerical experiments, several interesting phenomena were observed. The third load balancing strategy improved performance more than the first two other strategies. The second load balancing strategy, as a whole, resulted in only slightly improved performance. Finally, of the central node has larger processing power than the peripheral nodes, the first and third load balancing strategies produce equal performance improvement.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.2
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• pp.183-194
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• 2002

The clustering environment with heterogeneous workstations provides the cost effectiveness and usability for executing applications in parallel. Load balancing is considered a necessary feature for a cluster of heterogeneous workstations to minimize the turnaround time. Previously, static load balancing that assigns a predetermined weight for the processing capability of each workstation, or dynamic approaches which execute a benchmark program to get relative processing capability of each workstation were proposed. The execution of the benchmark program, which has nothing to do with the application being executed, consumes the computation time and the overall turnaround time is delayed. In this paper, we present efficient methods for task distribution and task migration, based on the relative load index. We designed and implemented a load balancing system for the clustering environment with heterogeneous workstations. Turnaround times of our methods and the round-robin approach, as well as the load balancing method using a benchmark program, were compared. The experimental results show that our methods outperform all the other methods that we compared.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.549-560
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• 2001

Cluster system provides attractive scalability in terms of compution power and memory size. With the advances in high speed computer network technology, cluster systems are becoming increasingly competitive compared to expensive MPPs (massively parallel processors). Load balancing is very important issue since an inappropriate scheduling of tasks cannot exploit the true potential of the system and can offset the gain from parallelization. In parallel processing program, it is difficult to predict the load of each task before running the program. Furthermore, tasks are interdependent each other in many ways. The dynamic load balancing algorithm, which evaluates each processor's load in runtime, partitions each task into the appropriate granularity and assigns them to processors in proportion to their performance in cluster systems. However, if the communication cost between processing nodes is expensive, it is not efficient for all nodes to attend load balancing process. In this paper, we restrict a processor that attend load balancing by the communication cost and the deviation of its load from the average. We simulate various models of the cluster system with parameters such as communication cost, node number, and range of workload value to compare existing load balancing methods with the proposed dynamic algorithms.

• Journal of Information Processing Systems
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• v.5 no.2
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• pp.69-76
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• 2009

Self healing systems are considered as cognation-enabled sub form of fault tolerance system. But our experiments that we report in this paper show that self healing systems can be used for performance optimization, configuration management, access control management and bunch of other functions. The exponential complexity that results from interaction between autonomic systems and users (software and human users) has hindered the deployment and user of intelligent systems for a while now. We show that if that exceptional complexity is converted into self-growing knowledge (policies in our case), can make up for initial development cost of building an intelligent system. In this paper, we report the application of AHSEN (Autonomic Healing-based Self management Engine) to in OKKAM Project infrastructure backbone cluster that mimics the web service based architecture of u-Zone gateway infrastructure. The 'blind' load division on per-request bases is not optimal for distributed and performance hungry infrastructure such as OKKAM. The approach adopted assesses the active threads on the virtual machine and does resource estimates for active processes. The availability of a certain server is represented through worker modules at load server. Our simulation results on the OKKAM infrastructure show that the self healing significantly improves the performance and clearly demarcates the logical ambiguities in contemporary designs of self healing infrastructures proposed for large scale computing infrastructures.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.29-32
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• 2012

전통적으로 컴퓨터의 성능은 중앙 연산 장치 (CPU)의 성능에 따라 좌지우지 되어 왔다. 하지만 CPU의 성능이 지속적인 발전을 거듭하여 무어의 법칙을 비교적 충실히 따라가고 있는 반면, 메모리의 성능은 근래 들어 더디게 발전되는 형국이다. 때문에, CPU와 메모리 간의 성능격차로 인해 메모리의 낮은 성능이 전체 시스템의 성능을 저하시키는 "Memory Wall Problem"은 점점 큰 문제로 대두되고 있다. 이러한 문제를 해결하기 위해 많은 연구에서 메모리 자체의 성능을 발전시키는 것은 물론 메모리 내부에 연산 처리 능력을 추가하여 시스템 전체의 성능을 향상 시키는 시도들을 해왔다. 이 논문에서는 이러한 Intelligent한 메모리 시스템에서의 SW Off-loading을 위한 성능 분석을 다룬다. 이전의 연구들이 주로 큰 단위의 Off-load를 다뤘던 것에 비해 이 논문에서는 작은 단위의 Off-load, 더 정확히는 어셈블리 수준의 Off-load의 효과에 대해 분석한다. 또한 현재의 어셈블리 수준의 Off-load의 한계를 지적하고 이를 극복하기 위한 루프 레벨 Off-load, 새로운 Technology와 아키텍쳐에 대해서도 소개한다.

• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.417-422
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• 2009

Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.440-443
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• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

• Journal of Korea Multimedia Society
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• v.11 no.7
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• pp.914-927
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• 2008

Grid database management systems are used for large data processing, high availability and data integration in grid computing. Furthermore the grid database management systems are in the use of manipulating the queries that are sent to distributed nodes for efficient query processing. However, when the query processing is concentrated in a random node, it will be occurred with imbalance workload and decreased query processing. In this paper we propose a load balancing method for query processing based on cache Management in grid databases. This proposed method focuses on managing a cache in nodes by cache manager. The cache manager connects a node to area group and then the cache manager maintains a cached meta information in node. A node is used for caching the efficient meta information which is propagated to other node using cache manager. The workload of node is distributed by using caching meta information of node. This paper shows that there is an obvious improvement compared with existing methods, through adopting the proposed algorithm.

• Transactions of Materials Processing
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• v.18 no.4
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• pp.323-328
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• 2009

The prediction of drawing load is very important in the drawing process. However, it is not easy to calculate the drawing load for the shape drawing process through a theoretical model because of a complex arbitrary final cross section shape. The purpose of this study is to predict drawing load in shape drawing process. The cross section of product is divided with small angle as much as similar with fan-shape. The drawing load of each section was calculated by theoretical model of round to round drawing process. And the shape drawing load was determined by summation of drawing load of each section. The effectiveness of the proposed method was verified through the FE analysis and shape drawing experiment. It had a good agreement between proposed method, FE analysis and experiment within about 3% errors.

• Journal of IKEEE
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• v.19 no.3
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• pp.455-459
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• 2015

This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.