• Journal of the Korea Society of Computer and Information
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• v.23 no.7
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• pp.19-26
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• 2018

This paper presents a structuring process of unstructured social network service (SNS) messages on rail services. We crawl messages about rail services posted on SNS and extract keywords indicating date and time, rail operating company, station name, direction, and rail service types from each message. Among them, the rail service types are classified by machine learning according to predefined rail service types, and the rest are extracted by regular expressions. Words are converted into vector representations using Word2Vec and a conventional Convolutional Neural Network (CNN) is used for training and classification. For performance measurement, our experimental results show a comparison with a TF-IDF and Support Vector Machine (SVM) approach. This structured information in the database and can be easily used for services for railway users.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2009.05a
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• pp.141-144
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• 2009

An injector plays an important role in the process of an efficient combustion in liquid-rocket engines (LRE). This paper is focused on the injection performance of a small LRE-injector by employing the spray characteristic parameters made up of the velocity, Sauter mean diameter, and turbulence intensity. An experimental investigation is carried out with the aid of a dual-mode phase Doppler anemometry (DPDA) according to the injection pressure variation and along transverse axis, spatially. The Weber number and Reynolds number are used to characterize the atomization and turbulence nature of injector spray.

• Journal of the East Asian Society of Dietary Life
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• v.11 no.3
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• pp.190-195
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• 2001

The objective of this study consists in finding the ways to make soybean cake (which is made of soaked soybean flour containing protein and lipid) a scientific and practical food even more easily. This study took a measurement of the change of pH, organic acid, microorganism, retrogradation and so soon. observing soybean cake prepared with soybean flour containing 6% of soybean oil at room temperature(19$^{\circ}C$) in two types of packaging, that is to say, $CO_2$ modified packing(CMP) and liner low density poly ethylene(LLDPE) packaging. As storing time went by, packed soybean cake didn't appeared in 12 days, either. Using modified atmosphere packaging soybean cake showed higer pH as well as less organic acid than unpacked. In addition, mould method makes water - activity lower, and it Puts a curb on the development of aerobic perishable microorganism and the retrogradation of rice cake. Unpacked soybean cake showed higher values than CMP Soybean Cake with enthalpy of retrogradation and the longer storing period the greater retrogradation process. Thus, storing or circulation period can be increased effectively without chemical or physical treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.16-21
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• 2007

A Dual-Path Voltage Multiplier for passive RFID Tags was proposed and fabricated by using a 0.25um CMOS process with additional steps for schottky diodes. The proposed circuit needs only 4 additional diodes, and the area increment compared to conventional one is negligible in multi-stage voltage multipliers. The simulation and measurement results show that the output power capability of proposed multiplier are about two times larger than the conventional half-wave multiplier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.471-476
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• 2015

This paper describes a CMOS hysteretic DC-DC buck converter with a constant switching frequency for mobile applications. The inherent problems of a large output ripple voltage that the conventional hysteretic DC-DC buck converters has faced have been resolved by using the proposed DC-DC buck converter which employed a ramp generator circuit to be able to increase a switching frequency. The proposed architecture enables the settling response time of charge pump circuit within the converter to become less than 6us suitable for mobile applications. The proposed DC-DC buck converter was implemented by using 0.35 um BCDMOS process and die size was $1.37mm{\times}1.37mm$. The measurement results showed that the proposed circuit received the input of 3.7 V and generated output of 1.2 V with the output ripple voltages less than 20 mV under load currents of 100~400 mA at the fixed switching frequency of 2 MHz. The maximum efficiency of the proposed hysteretic buck converter was measured to be around 93%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.11-16
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• 2008

In this paper, firstly we made of the rapid thermal processor equipment with the specifically useful structure to measure wafer stress. Secondly we made of the laser interferometry to inspect the wafer surface curvature based on the large deformation theory. And then the wafer surface fringe image was obtained by experiment, and the full field stress distribution of wafer surface comes into view by signal processing with thining and pitch mapping. After wafer was ground by 1mm and polished from the back side to get easily deformation, and it was heated by three to four times thermal treatments at about 1000 degree temperature. Finally the severe deformation between wafer before and after the heat treatment was shown.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.223-228
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• 2014

In this paper, a curriculum-based electronic design project with a improved training kit is discussed. Students can raise the practical ability for comprehension and analysis of electronic circuits by the design and assembly of electronic components and measurement practice and learning the process closely. The products of this paper can be utilized as hands-on training for increasing confidence in the improving education for creative practical electronic design ability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.