• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.10
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• pp.1120-1124
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• 2004

Recently, Plasma Display Panel(PDP) has been in the spotlight as one of the next generation flat-panel-display device. However, it has several drawbacks like the low contrast ratio and the low luminance. In this study, a new address waveform is suggested to improve the priming effect and contrast ratio at the address period in the Address Display period Separated(ADS) method. We modified waveform, instead of a conventional waveform, to an address period, for operating on the Plasma Display Panels, which used the conventional gas [He-Ne-Xe〕. When the ramp pulse is added to the address period at the sustain electrode, it is improved on the priming effect and contrast ratio.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1544-1545
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• 2006

In this paper, we present a new reset waveform for a large-sustain-gap structure in at PDPs. In the driving of the large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address being a cathode, which causes lots of trouble in stabilizing a reset discharge. To solve these problems, we use the square pulse instead of the conventional rising ramp pulse. Before making a strong discharge between the address (cathode) and scan (anode) electrodes, we make a priming discharge between the address (anode) and the scan (cathode) electrodes to stabilize the strong discharge in which the address electrodes are the cathode. With this scheme, we obtained 60V minimum address voltage and 145V maximum address voltage in $250{\mu}m$ and $350{\mu}m$ gap structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.72-75
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• 2003

Effects of delay and panel temperature on the discharge time lag and the controllability of weak discharge mode were studied under single cell driving circumstances of ac PDP. It was found that sufficient number of priming particle is necessary for inducing weak discharge in ramp voltage driving. Discharge time lag was reduced dramatically under elevated panel temperature condition It is speculated that decrement of discharge time lag at the high temperature is related to the reduction of diffusion loss of charged particles during the after glow.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1686-1688
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• 2003

Effects of delay and panel temperature on the discharge time lag and the controllability of weak discharge mode were studied under single cell driving circumstances of at PDP. It was found that sufficient number of priming particle is necessary for inducing weak discharge in ramp voltage driving. Discharge time lag was reduced dramatically under elevated panel temperature condition. It is speculated that decrement of discharge time lag at the high temperature is related to the reduction of diffusion loss of charged particles during the after glow.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.197-197
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• 2000

AC-PDP의 구동 요소 중 중요한 것은 벽전하와 그로부터 유도되는 벽전압, 그리고 프라이밍입자(priming partical)의 밀도 변화라고 할 수 있다. 패널의 초기화가 전구간의 방전을 좌우하기 때문에 초기화 펄스의 기울기에 따른 방전현상을 이해하고자 각 구간에서의 전기-광학적 특성과 함께 휘도와 효율의 관점에서 연구 조사하였다. 본 실험에서 사용한 reset 펄스파형은 셀의 방전개시전압과 인가전압사이의 차이가 적고, 초기 프라이밍 입자와 단위시간당 전자에 공급되는 에너지가 적은 램프형태의 초기화 펄스를 사용하였다. 실험장치는 VDS(versatile driving simulator)시스템을 이용하였다. 실험결과 reset의 기울기가 커질수록 반응시간이 빨라지며, 약방전의 형태를 고속이미지로 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.135-139
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• 2015

The address discharge time lags are investigated in each subfield time in AC plasma display panel and a modified driving waveform is proposed to reduce the address discharge time lag by applying different additional scan voltage under no misfiring discharge production. The weak plasma discharge in AC PDP is generated by applying high positive-going ramp waveform to the scan electrode during the first reset period and that induce the production of the priming particle and wall charge. Because the wall charge becomes the wall voltage in a cell, the wall plus external address voltage produce the address discharge. However, as the wall charge in a cell is gradually disappeared as time passed, the address discharge time in the subfield time for 1 TV frame is lagged. In the first subfield time, the address discharge is faster produced than the other subfield time because the wall charge are much remained by the high positive-going ramp voltage during the reset period in the first subfield time. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the total address discharge time lags are shortened by applying the different additional scan voltage during the address period in each the subfield time.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.95-96
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• 2009

It is analyzed how the Plasma - MgO surface interaction, driving waveform and their inter-relation can cause misfiring. Developing of glow discharge mode during the ramp reset due to lack of priming particles was suggested as one of the important misfiring sources. It is also shown that simple modification of reset waveform can considerably reduce misfiring probability.