• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2569-2574
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• 2010

In this paper, we introduce an efficient energy management using a notion of virtual energy system for shared solar-powered sensor network. Virtual energy system is an abstraction that allows sensor network applications on a node to reserve their own fractions of the shared solar cell and the shared rechargeable battery, hence achieving logically partition of a shared renewable power source. Our results show that our design and implementation are reliable, lightweight and efficient, allowing proper isolation of energy consumption among applications.

• Journal of Communications and Networks
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• v.10 no.1
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• pp.28-37
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• 2008

In this paper, we investigate the problem of minimizing the average transmission power of users while guaranteeing the average delay constraints in time-varying uplink channels. We design a scheduler that selects a user for transmission and determines the transmission rate of the selected user based on the channel and backlog information of users. Since it requires prohibitively high computation complexity to determine an optimal scheduler for multi-user systems, we propose a low-complexity scheduling scheme that can achieve near-optimal performance. In this scheme, we reduce the complexity by decomposing the multiuser problem into multiple individual user problems. We arrange the probability of selecting each user such that it can be determined only by the information of the corresponding user and then optimize the transmission rate of each user independently. We solve the user problem by using a dynamic programming approach and analyze the upper and lower bounds of average transmission power and average delay, respectively. In addition, we investigate the effects of the user selection algorithm on the performance for different channel models. We show that a channel-adaptive user selection algorithm can improve the energy efficiency under uncorrelated channels but the gain is obtainable only for loose delay requirements in the case of correlated channels. Based on this, we propose a user selection algorithm that adapts itself to both the channel condition and the backlog level, which turns out to be energy-efficient over wide range of delay requirement regardless of the channel model.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.285-287
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• 2014

This paper describes a design of area-efficient/low-power cryptographic processor for lightweight block cipher algorithm HIGHT which was approved as a cryptographic standard by KATS and ISO/IEC. The HIGHT algorithm which is suitable for the security of IoT(Internet of Things), encrypts a 64-bit plain text with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we adopt 32-bit data path and optimize round transform block and key scheduler to share hardware resources for encryption and decryption.

• Journal of Korea Multimedia Society
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• v.17 no.8
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• pp.1012-1019
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• 2014

The emerging smart utility networks (SUN) provide two-way communications between smart meters and smart appliances for purpose of low power usage, low cost, and high reliability. This paper deals with a bandwidth-efficient communication method based on the hidden pilot-aided scheme using a precoder in downlink SUN suitable for high-rate multimedia applications. With the aid of the design of a precoder and a superimposed hidden pilot, it is possible to estimate the channel without loss of bandwidth. In the channel estimation procedure, the inevitable data interference, which degrades the performance of channel estimation, can be reduced by the precoder design with an iterative scheme. Computer simulations show that the proposed scheme outperforms the conventional method in terms of achievable data rate, especially when a large number of subcarriers are employed.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.75-76
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• 2016

This paper proposes a power factor correction circuit with a high efficiency over a wide load range characteristics for a communication power supply. And the characteristic verification is applied to produce a design of prototype. Power factor correction circuit can reduce conduction losses by applying Bridgeless Boost Converter for efficiency. Over a wide load range to maintain the efficient, the control method of a PWM controller is divided by two sections according to the load area. In the low-load region, it was reduced switching losses by applying the critical conduction mode control method. On the other hand, in the heavy-load area, the hysteresis current control method is used to maintain the high efficiency over a wide load range by limiting the peak noise of the inductor.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.121-124
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• 2003

In this paper, a novel PFC AC / DC converter is presented to be appropriate for AC PDP's power driving system. The conventional PFC AC / DC converter has independent power stages and controllers for their switching respectively, which should have increased price, size on manufacturing and decreased its efficiency as well. So this advanced Single-Stage Power Factor Corrector is presented and verified through spice simulation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.9
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• pp.459-466
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• 2000

The performance of a commercialized power system stabilizer (PWX-600) for a single hydro-turbine generator and infinite bus system has been investigated using Real Time Digital Simulator (RTDS) in this paper. The test system was composed of RTDS, three phase voltage/current amplifier and the PSS. The test scheme provided a very efficient way to verify the design and control performance of a PSS to be applied to real power system. The scheme can also be applied to verify in real time the performance of hardware and software of power system controllers for FACTS and protective relays effectively.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1322-1324
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• 2001

FuelCell/Battery hybrid power systems were studied to develop high efficient zero-emission fuel cell electric vehicles. Fuel cells were used as an auxiliary energy source and batteries were used as a transient power source. The fuel cell system is used to supply the average power demand. Dynamic response of the hybrid systems was simulated using PSPICE program and also tested experimentally. The results can be used to design the interface module and to determine the power requirement between the fuel cell unit and the battery pack.

• ETRI Journal
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• v.25 no.5
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.