• Title/Summary/Keyword: power strap

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A Study on Gate driver with Boot-strap chain to Drive Multi-level PDP Driver Application (Multi-level PDP 구동회로를 위한 Gate driver의 Boot-strap chain에 관한 연구)

  • Nam, Won-Seok;Hong, Sung-Soo;SaKong, Suk-Chin;Roh, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.2
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    • pp.120-126
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    • 2006
  • A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

Stable Power Plan Technique for Implementing SoC (SoC 구현을 위한 안정적인 Power Plan 기법)

  • Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.12
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    • pp.2731-2740
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    • 2012
  • ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

A study on gate driver with Boot-strap chain to drive Multi-level PDP driver application (Multi-level을 사용한 PDP 구동회로를 위한 Gate driver 의 Boot-strap chain 에 관한 연구)

  • Nam, Won-Seok;Kim, Jun-Hyoung;Song, Suk-Ho;Roh, Chung-Wook;Hong, Sung-Soo;SaKong, Suk-Chin
    • Proceedings of the KIPE Conference
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    • 2005.07a
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    • pp.99-101
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    • 2005
  • A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the drivel board can be reduced.

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A Study on the Effect of GND Condition on CISPR25 Radiation Emission Test (GND조건이 CISPR25 복사방출 시험에 미치는 영향에 관한 연구)

  • Yoon, Jin-sang;Hong, ik-pyo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2018.05a
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    • pp.404-407
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    • 2018
  • - A car is a means of transporting passengers or cargo on the ground by transmitting power from the engine to the wheels. In the past, automobiles started from internal combustion engines have recently been introduced with hybrid electric vehicles and pure electric vehicles. As a result, the deployment of high-tech electrical and electronic products is inevitably increased due to the development of technology and stability of various parts, resulting in a more complicated and diversified electromagnetic environment. CISPR 25 is conducting research on the test method for electromagnetic noise. In order to analyze the noise pattern according to the GND condition required in the radiation emission test, various conditions are applied for comparison. 2 Page - General characteristics of EMI chambers, techniques for testing and measuring equipmen 3 Page - RE test : Analysis of Noise due to Ground Strap Change when Sample is in Center, Analysis of Noise due to Ground Strap Changes when the Sample is not in the Center.

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차세대 위성용 탑재컴퓨터 설계

  • Kwon, Ki-Ho;Kim, Day-Young;Choi, Seung-Woon;Lee, Yun-Ki;Lee, Jong-In;Kim, Hak-Jung
    • Aerospace Engineering and Technology
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    • v.4 no.2
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    • pp.79-87
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    • 2005
  • This paper describes a new on-board computer design for the next generation satellite. The new on-board computer utilizes centralized processing architecture with MCMERC325C CPU based on functional modular design concepts. The on-board computer consists of PM32 Module, TC-TM Module, IO Module and Power module. The IEEE-1355 DS/DE, or SpaceWire, provides a standard communication interface between module. It also provides simple cross-strap design for redundancy management and increases re-usability of the modules.

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Performance Evaluation of Vane Motor Driven by Monopropellant (일원추진제 구동 터빈 출력장치의 성능평가)

  • Hong, Deuk-Eui;Ryu, Ga-Ram;Han, Seung-Ho
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.11 no.5
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    • pp.35-41
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    • 2012
  • Liquified hydrogen peroxide as a monopropellant is drawing an attention as a power generating energy source for a machine requiring simple and light weight structure. The liquified hydrogen peroxide is attracted due to its outstanding applicability because it doesn't require an oxidizer and discharge a hazardous product. For the further industrial applications, however, a feasibility study should be carried out carefully in the aspect of the specific power density. In this study, a prototype of vane motor driven by the liquified hydrogen peroxide with high density of upper 95% was developed and its performance characteristic such as a specific power density was estimated via measuring pressure and rotation speed of the vane motor. The specific power density obtained by numerical simulation using FSI analysis supported by experimental results was up to $0.02kW/kg_{f}$, which reaches at the level of the latest developed fuel cell.

Active control of amplitude and phase of high-power RF systems in EAST ICRF heating experiments

  • Guanghui Zhu;Lunan Liu;Yuzhou Mao;Xinjun Zhang;Yaoyao Guo;Lin Ai;Runhao Jiang;Chengming Qin;Wei Zhang;Hua Yang;Shuai Yuan;Lei Wang;Songqing Ju;Yongsheng Wang;Xuan Sun;Zhida Yang;Jinxin Wang;Yan Cheng;Hang Li;Jingting Luo
    • Nuclear Engineering and Technology
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    • v.55 no.2
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    • pp.595-602
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    • 2023
  • The EAST ICRF system operating space has been extended in power and phase control with a low-level RF system for the new double-strap antenna. Then the multi-step power and periodic phase scanning experiment were conducted in L-mode plasma, respectively. In the power scanning experiment, the stored energy, radiation power, plasma impedance and the antenna's temperature all have positive responses during the short ramp-ups of PL;ICRF. The core ion temperature increased from 1 keV to 1.5 keV and the core heating area expanded from |Z| ≤ 5 cm to |Z| ≤ 10 cm during the injection of ICRF waves. In the phasing scanning experiment, in addition to the same conclusions as the previous relatively phasing scanning experiment, the superposition effect of the fluctuation of stored energy, radiation power and neutron yield caused by phasing change with dual antenna, resulting in the amplitude and phase shift, was also observed. The active control of RF output facilitates the precise control of plasma profiles and greatly benefits future experimental exploration.

Safeguard Memory Operation for LEO Stellite (저궤도위성 세이프가드 메모리 운영)

  • Chae, Dong-Seok;Yang, Seung-Eun;Cheon, Yee-Jin
    • Proceedings of the Korea Information Processing Society Conference
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    • 2012.11a
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    • pp.8-10
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    • 2012
  • 위성을 전체적으로 제어하는 탑재소프트웨어가 동작하는 주 메모리와는 별도로 세이프가드 메모리가 있다. 세이프가드 메모리는 주로 위성의 장애관리를 위해 사용되는 것으로 프로세서 리셋 시에 전체적으로 초기화가 수행되는 주 메모리와는 달리 별도의 전원을 사용하여 항상 Power-ON 상태를 유지하고 주/부 2개의 메모리가 주/부 프로세서와 Cross-Strap으로 연결되어 어느 프로세서에서든 접속이 가능하도록 구성되어 있다. 위성에 심각한 장애가 발생하여 정상적인 운영이 불가능한 경우, 위성은 Fail-over 과정을 거치게 되는데, Fail-over 과정에서 2개의 세이프가드 메모리의 비상운영데이터 영역에 장애 발생원인 및 프로세서 리셋 이후에 필요한 정보들을 기록하고, 미리 정해진 Backup 하드웨어를 이용하여 시스템 초기화가 수행된다. Backup 하드웨어를 통하여 프로세서가 정상적으로 Boot-up되면 세이프가드 메모리에 저장된 비상운영데이터를 이용하여 위성의 장애발생 원인을 파악하고, 정상운영모드로 복귀하는 절차를 거치게 된다. 본 논문은 저궤도 위성에서 사용되는 세이프가드 메모리 운영방식에 대해 기술한 것이다.

3-D Simulation of Pyroelectric IR Sensor and Design of Optimized Peripheral Circuit (초전형 적외선 센서의 3차원 모델링과 최적화된 주변회로 설계)

  • Min, Kyung-Jin;Kang, Seong-Jun;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.10
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    • pp.33-41
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    • 2000
  • Pyroelectric characteristics such as voltage responsivity, noise equivalent power and detectivity are modeled 3-dimensionaly considering th interaction of each parameters. Also, the circuit is designed to set up the frequency band width and the signal amplification of the pyroelectric IR sensor. The case of low frequency region shows that the voltage response increases with the independence of the sensor area as the thickness decreases. In the high frequency region, it is found that the voltage response with the load resistor of 20$G{\Omega}$ increases with the independence of the sensor thickness as the sensor area decreases. In the low frequency region, the detectivity becomes excellent at th load resistor of 20$G{\Omega}$, the sensor area larger than $4{\times}10^{-10}m^2$ and the sensor thickness thinner than $1{\times}10^{-5}m$, while, in the high frequency region, it shows high value at the sensor thickness thinner than $1{\times}10^{-5}m$ and the sensor area smaller than $2{\times}10^{-10}m^2$ with the independence of the load resistor. In the circuit design, quasi-boot-strap circuit is employed, in which a single op-amp is connected to the drain of JFFT. Desirable frequency band width, amplification rate and the remarkable drop of noise of about 56% from that of conventional circuits with double op-amps are obtained.

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