• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.317-320
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• 2000

This paper proposes a voltage compensation method to improve the control performance of B4 inverter which is studied for low-cost drive systems. The B4 inverter employs only four switches and it has a center-tapped connection in the split dc-link capacitors to one phase of a three-phase motor. In the B4 topology unbalan-cd three-phase voltages will be generated by the dc link voltage ripple. To solve this problem we present a voltage compensation method which adjusts switching times considering dc link voltage ripple. The proposed method is verified by simulation results,

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.248-249
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• 2013

본 논문에서는 개별적인 MPPT 제어가 가능한 단상 DC-버스 분산형 인버터의 구조 및 제어 방식에 대해 소개한다. 본 인버터는 H-브릿지 인버터에서 직류단이 분리된 형태이며, 다수의 태양광 패널의 MPPT 제어가 가능하다. 본 논문에서는 제안된 인버터의 계통 발전 방식과 함께 각 태양광 패널의 전력 분배 제어에 대해 논의하며, 모의실험을 통해 제안된 방식의 성능을 확인한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.359-369
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• 2003

We present efficient generalized algorithms for all-to-all personalized communication operations in a 2D torus. All-to-all personalized communication, or complete exchange, is at the heart of numerous applications, such as matrix transposition, Fast Fourier Transform(FFT), and distributed table lookup. Some algorithms have been Presented when the number of nodes is power-of-2 or multiple-of-four form, but there has been no result for general cases yet. We first present complete exchange algorithm called multiple-Hop-2D when the number of nodes is in the form of multiple-of-two. Then by extending this algorithm, we present two algorithms for an arbitrary number of nodes. Split-and-Merge algorithm first splits the whole network into zones. After each zone performs complete exchange, merge is applied to finish the desired complete exchange. By handling extra steps in Double-Hop-2D algorithm, Modified Double-Hop-2D algorithm performs complete exchange operation for general cases. Finally, we compare the required start-up time for these algorithms.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.1
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• pp.105-111
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• 2010

This article studies the design of DC-DC Converter to convert low-voltage energy sources generated from renewable power like battery power, photovoltaic power, or fuel cells into high-voltage ones. The circuit topology of H-bridge Converter to convert input voltage, 24[V], into out voltage, 400[V], was realized through applying phase shift angle control so as to manage electric power and voltage in the output side. The advantages of the converter system suggested are the low cost as well as current stress reduction, high efficiency, reliability, and simplified maintenance. It is also found that the system is highly useful to produce residential electric power.

• Journal of Power Electronics
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• v.15 no.2
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• pp.389-398
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• 2015

This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.378.2-378.2
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• 2014

We have investigated optical characteristics of $p-Ge_{0.99}Sn_{0.01}$ and Ge films grown on Si substrates using photoreflectance (PR) spectroscopy. The $Ge_{0.99}Sn_{0.01}$ and Ge films were grown by using an ultra-high vacuum chemical vapor deposition and molecular beam epitaxy methods, respectively. PR spectra were measured at 25 K and an extended InGaAs detector was used. By comparing $Ge_{0.99}Sn_{0.01}/Si$ and Ge/Si spectra, we observed the signals related to direct transition and split-off band of $Ge_{0.99}Sn_{0.01}$. The transition energies of $Ge_{0.99}Sn_{0.01}$ and Ge films were approximately 0.74 and 0.84 eV, respectively. Considering the shift of split-off band transition of $Ge_{0.99}Sn_{0.01}$, we suppose that the transition at 0.74 eV is attributed to direct transition between ${\Gamma}$ band and valence band. The temperature- and excitation power-dependent PR spectra were also measured.

• Journal of the Korean Society of Clothing and Textiles
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• v.5 no.2
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• pp.35-40
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• 1981

This study aims at finding appropriate adhesive conditions with special regard the material of 'fusible padding cloth inter ling' was frequently used for leather. As for leather material, pig suede, sheep suede were selected and drum dyed, cow split, napa have also been used. Mixed spinning non-woven fabric (polyester $50\%$, nylon $50\%$) were used as for padding cloth. Experimental appearance has been observed under the following adhesive conditions: Temperature of press were devided four levers; $120^{\circ}C$, $130^{\circ}C$, $140^{\circ}C$, $150^{\circ}C$, respectively. Adhesive time has been limited 5, 10, 15 second each. And the pressure has been conditioned as $0.2kg/cm^2$ continuously. After all this experiment, it was discovered that the material which had long contact with low temperature conditions has similar adhesive power to material that has short contact with high temperature conditions. There is a great difference according to the leather's dying process, the finishing method of the cloth, and the part of leather surface. The best condition for suede are $140^{\circ}C$, $150^{\circ}C$, at 10 seconds. and for D/D, NAPA, $130^{\circ}C$, at 10 seconds. Although the conditions of $150^{\circ}C$, at 15 seconds was possible for split, the process time can be shortened according to the increase of temperature.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.2
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• pp.216-224
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• 2013

This paper describes dual inverter drive for a fractional-slot concentrated winding permanent magnet synchronous machine (PMSM). PMSMs are widely used in many applications from small servo motors to few megawatts generators thanks to its high efficiency and torque density. Especially, fractional-slot concentrated winding PMSM is very popular in the applications where wide operation range is required because it shows very wide constant power speed ratios. High speed operation, however, requires lots of negative daxis current for reducing back-EMF regardless of output torque. Field weakening current does not contribute to the torque generation in surface mounted PMSM case and causes inverter and copper loss. To reduce the losses from field weakening current, this paper proposes PMSM with split stator and parallel dual inverter drive. Proposed parallel dual inverter drive reduces back-EMF and enables efficient drive at high speed and light load situation. Control strategy of proposed dual inverter system is established through loss analysis and simulation. Proposed concept is verified with practical experiment.