• Title/Summary/Keyword: power scalable

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Design and Implementation of a Power Aware Scalable Pipelined Booth Multiply & Accumulate Unit (소비전력 인지형 곱셈 연산 누적기의 설계 및 구현)

  • Shin, Min-Hyuk;Lee, Han-Ho
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.573-574
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    • 2006
  • A low-power power-aware scalable pipelined Booth recoded multiply & Accumulate unit (PA-MAC) detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication and accumulation operation. The multiplication mode is determined by the dynamic - range detection unit. For the computations, although an area of the proposed PA-MAC is lager than a non-scalable MAC respectively, the proposed PA-MAC proves to be globally more power efficient than a non-scalable MAC.

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Power-Scalable, Sub-Nanosecond Mode-Locked Erbium-Doped Fiber Laser Based on a Frequency-Shifted-Feedback Ring Cavity Incorporating a Narrow Bandpass Filter

  • Vazquez-Zuniga, Luis Alonso;Jeong, Yoonchan
    • Journal of the Optical Society of Korea
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    • v.17 no.2
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    • pp.177-181
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    • 2013
  • We present an all-fiberized power-scalable, sub-nanosecond mode-locked laser based on a frequency-shifted-feedback ring cavity comprised of an erbium-doped fiber, a downshifting acousto-optic modulator (AOM), and a bandpass filter (BPF). With the aid of the frequency-shifted feedback mechanism provided by the AOM and the narrow filter bandwidth of 0.45 nm, we generate self-starting, mode-locked optical pulses with a spectral bandwidth of ~0.098 nm and a pulsewidth of 432 to 536 ps. In particular, the output power is readily scalable with pump power while keeping the temporal shape and spectral bandwidth. This is obtained via the consolidation of bound pulse modes circulating at the fundamental repetition rate of the cavity. In fact, the consolidated pulses form a single-entity envelope of asymmetric Gaussian shape where no discrete internal pulses are perceived. This result highlights that the inclusion of the narrow BPF into the cavity is crucial to achieving the consolidated pulses.

Joint resource optimization for nonorthogonal multiple access-enhanced scalable video coding multicast in unmanned aerial vehicle-assisted radio-access networks

  • Ziyuan Tong;Hang Shen;Ning Shi;Tianjing Wang;Guangwei Bai
    • ETRI Journal
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    • v.45 no.5
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    • pp.874-886
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    • 2023
  • A joint resource-optimization scheme is investigated for nonorthogonal multiple access (NOMA)-enhanced scalable video coding (SVC) multicast in unmanned aerial vehicle (UAV)-assisted radio-access networks (RANs). This scheme allows a ground base station and UAVs to simultaneously multicast successive video layers in SVC with successive interference cancellation in NOMA. A video quality-maximization problem is formulated as a mixed-integer nonlinear programming problem to determine the UAV deployment and association, RAN spectrum allocation for multicast groups, and UAV transmit power. The optimization problem is decoupled into the UAV deployment-association, spectrum-partition, and UAV transmit-power-control subproblems. A heuristic strategy is designed to determine the UAV deployment and association patterns. An upgraded knapsack algorithm is developed to solve spectrum partition, followed by fast UAV power fine-tuning to further boost the performance. The simulation results confirm that the proposed scheme improves the average peak signal-to-noise ratio, aggregate videoreception rate, and spectrum utilization over various baselines.

Scalable Video Coding with Low Complex Wavelet Transform (공간 웨이블릿 변환의 복잡도를 줄인 스케일러블 비디오 코딩에 관한 연구)

  • Park, Seong-Ho;Kim, Won-Ha;Jeong, Se-Yoon
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.298-300
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    • 2004
  • In the decoding process of interframe wavelet coding, the inverse wavelet transform requires huge computational complexity. However, the decoder may need to be used in various devices such as PDAs, notebooks, PCs or set-top Boxes. Therefore, the decoder's complexity should be adapted to the processor's computational power. A decoder designed in accordance with the processor's computational power would provide optimal services for such devices. So, it is natural that the complexity scalability and the low complexity codec are also listed in the requirements for scalable video coding. In this contribution, we develop a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining almost the same coding efficiency as the conventional spatial wavelet transform. In addition, the proposed method may alleviate the ringing effect for certain video data.

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A New Coding Technique for Scalable Video Service of Digital Hologram (디지털 홀로그램의 적응적 비디오 서비스를 위한 코딩 기법)

  • Seo, Young-Ho;Bea, Yoon-Jin;Lee, Yoon-Hyuk;Choi, Hyun-Jun;Yoo, Ji-Sang;Kim, Dong-Wook
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.92-103
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    • 2012
  • In this paper, we discuss and propose a new algorithm of coding technique for scalably servicing holographic video in various decoding environment. The proposed algorithm consists of the hologram-based resolution scalable coding (HRS) and the light source-based SNR scalable coding (LSS). They are classified by the method generating and capturing hologram. HRS is a scalable coding technique for the optically captured hologram and LSS is one for the light source before generating hologram. HRS can provide the scalable service of 8 steps with the compression ratio from 1:1 to 100:1 for a $1,024{\times}1,024$ hologram. LSS can also provide the various service depending on the number of the light source division using lossless compression. The proposed techniques showed the scalable holographic video service according to the display with the various resolutions, computational power of the receiving equipment, and the network bandwidth.

Circulating Current Reduction Method Using High Frequency Voltage Compensation in Asynchronous Carriers for Modular Scalable Inverter System (Modular Scalable Inverter System에서 캐리어 비동기시 고주파 전압 보상을 이용한 순환전류 저감 기법)

  • Choi, Seung-Yeon;Kang, Shin-Won;Im, Jun-Hyuk;Kim, Rae-Young
    • The Transactions of the Korean Institute of Power Electronics
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    • v.24 no.2
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    • pp.71-77
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    • 2019
  • This study proposes a circulating current reduction method that uses high-frequency voltage compensation when carrier phase difference occurs between two inverters in MSIS. In MSIS, inverters are configured in parallel to increase power capacity and to increase efficiency by using inverters only as needed. However, in the parallel inverter structure, circulating current is inevitably generated. Circulating current increases the stress on the switch, adversely affects the current control performance, and renders load sharing difficult. The proposed method compensates for the output voltage reference of the slave module by using the high-frequency voltage so that the switching pattern of each module is matched even in asynchronous carriers. The validity of the proposed method is verified by simulations and experiments with 600 W IPMSM.

Modification of an Analysis Algorithm for DC Power Systems Considering Scalable Topologies

  • Lee, Won-Poong;Choi, Jin-Young;Park, Young-Ho;Kim, Soo-Nam;Won, Dong-Jun
    • Journal of Electrical Engineering and Technology
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    • v.13 no.5
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    • pp.1852-1863
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    • 2018
  • Direct current(DC) systems have recently attracted attention due to the increase in DC loads and distributed generations, such as renewable energy sources. Among these technologies, there has been much research into DC distribution systems or DC microgrids. Within this body of research, the main topics have been about optimum control and operation methods in terms of improving power efficiency. When DC systems are controlled and operated using power electronic devices such as converters, it is necessary to design and analyze them by considering the power electronics sections. For this reason, we propose a scalable DC system analysis algorithm, which considers various system configurations depending on the operating mode and location of the converter. The algorithm consists of power flow fault current calculations, and the results of the algorithm can be used for designing DC systems. The algorithm is implemented using MATLAB with defined input and output data. The verification of the algorithm is mainly performed using ETAP software, and the accuracy of the algorithm analysis can be confirmed through the results.

Circulating Current Reduction Using High Frequency Voltage Compensation in Carrier Asynchronous for Modular Scalable Inverter System (Modular Scalable Inverter System에서 캐리어 비동기시 고주파 전압 보상을 이용한 순환전류 저감기법)

  • Choi, Seung-Yeon;Kang, Shin-Won;Im, Jun-Huk;Kim, Rae-Yong
    • Proceedings of the KIPE Conference
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    • 2018.07a
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    • pp.30-32
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    • 2018
  • 본 논문은 Modular Scalable Inverter System(MSIS)에서 두 인버터 간에 캐리어 위상차로 인해 순환전류가 발생할 시 고주파 전압 보상을 이용한 순환전류 저감기법을 제안한다. MSIS는 인버터를 병렬로 구성하여 전력용량을 증가시키고 필요에 따라 선택적으로 사용하여 효율을 높인다. 하지만 병렬 인버터 구조에서는 필연적으로 순환전류가 발생하여 고주파 전압 보상을 이용하여 두 인버터가 동일한 스위칭 패턴을 출력하게 하여 주파수 성분의 순환전류를 저감한다. 제안한 방법의 유효성은 600W IPMSM를 부하로 한 MSIS 축소 모델에서 시뮬레이션을 통해 검증하였다.

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