• Journal of Institute of Control, Robotics and Systems
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• v.11 no.5
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• pp.393-397
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• 2005

When a real-time image processing application is implemented with a general-purpose computer, CPU (Central Processing Unit) is usually heavily loaded and in many cases that CPU alone cannot meet the real-time requirement at all. Most modern computers are equipped with powerful Graphics Processing Units (GPUs) to accelerate graphics operations. There is a trend that the power of GPU outgrows that of CPU. If we take advantage of the powerful GPU for more general operations other than pure graphics operations, the processing time can be reduced. In this study, we will present techniques that apply GPU to general operations such as image processing procedures. Our experiment results show that significant speed-up can be achieved by using GPU.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.337-338
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• 2014

본 논문에서는 배터리 셀 간의 빠른 전하 균일화를 위한 새로운 셀 밸런싱 회로를 제안한다. 대칭적인 다권선 변압기를 이용하는 밸런싱 회로의 경우 셀들 간의 밸런싱 전류의 크기가 회로 내부 저항 및 변압기의 누설 인덕턴스에 의해 크게 제약 받고, 배터리 셀 간의 밸런싱이 이루어짐에 따라 충방전 전류가 감소한다는 단점이 있다. 본 논문에서는 보조 회로를 이용하여 밸런싱 전류를 부스트 업 시켜 빠르게 셀 간의 전하 밸런싱을 맞추어주는 회로를 제안한다. 이를 통해 회로 내부 저항의 영향을 줄이고 일정한 충방전 전류를 흘려보냄으로 빠르게 셀 전하들의 밸런싱을 맞출 수 있다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.355-356
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• 2012

본 논문은 배터리 셀 전압의 균등화에 대한 새로운 회로를 제안한다. 제안한 회로는 확장된 다권선 변압기를 이용한 회로로 변압기 사이에 있는 권선을 연결하여 모듈 간의 밸런싱 동작이 이루어지게 하는 회로이다. 밸런싱 성능을 분석하기 위하여 Cantilever 변압기 모델을 사용하였는데 이 모델을 통하여 모듈 간의 밸런싱 편차를 도출하였다. 기존의 회로와는 대조적으로 이 제안된 회로는 모듈화 및 제어가 쉽고 무엇보다도 배터리 수에 제한이 없다는 점이 장점이다. 이것은 고전압을 요구하는 하이브리드 전기 자동차(HEV)와 같은 어플리케이션에서의 밸런싱된 많은 직렬 연결된 배터리 셀 전압에 중요한 이점들이 될 수 있다. 본 논문에서는 이 회로의 타당성을 검증하기 위하여 이론적으로 분석하고 6개의 배터리 셀들을 이용하여 시뮬레이션을 실시하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.419-428
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• 1986

While three most important aspects of line codes are the de-free, the minimum-bandwidth, and the self-clocking properties, the only TIBr, VMDBr, RMD3r, RMD4r codes possess all of these properties. This paper is to report the results of an experimental performance study of VMDB5. The encoder and decoder of VMDB5 and the pulse shaper have been inplemented. Power spectra, eye patterns, and error probabilities are experimentally measured, confirming the theoreticla performance predictions. It has been observed that the NRZ pulse shaping reliable transmission is possible with no extra equalization even in teh case when the -3dB channel bandwith is only half the Nyquist bandwidth.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.3-8
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• 2013

In CDMA-based systems, recently, researches on chip-level equalization have been studied in order to improve receiving performance when supporting high-rate data services. In this paper, we consider a chip-level LMMSE (linear minimum mean-squared error) receiver for D-TxAA (dual stream transmit antenna array) based single stream HSDPA MIMO systems using precoding weights. First, we will derive precoding weights for maximizing the total instantaneous received power. We will also analyze the effects of both transmit delay of precoding weights and mobile velocity on chip-level LMMSE receivers, which is verified through computer simulations in various mobile channel environments.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.393-400
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• 2012

The modularized equalizers normally use additional components among the modules in the long series-connected lithium-ion battery string. In these approaches, the overall systems are heavy, bulky, and high-priced. Furthermore, the losses related to additional components decrease the system efficiency. To avoid these problems, a modularized equalizer, which has no additional components among the modules, is required. This paper proposes a novel control scheme using the magnetizing energy of the multi-winding transformer for the module equalization. In this scheme, the high duty cycle is applied to the module where the voltage is higher than the reference voltage and the low duty cycle is applied to the module where the voltage is lower than the reference voltage. Due to the different duty cycle, more electric charges are transferred from high voltage module to the low voltage module during the turn-off switching interval. Using the proposed control scheme, the equalizer system does not suffer from the size, cost, and loss related to the modularization. The experimental results are provided to verify the effectiveness of the proposed modularized equalizer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.19-28
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• 2000

The parallel inverter is widely utilized because of its fault-tolerance capability, high-current output at constant voltages and system modularity. The conventional paralled inverter usually employes an active and reactive power control or a frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes novel control scheme for equalization of output power between the parallel connected inverters. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed constrol scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Journal of Navigation and Port Research
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• v.36 no.3
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• pp.169-173
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• 2012

In this paper, we propose an equalizer to minimize the inter-symbol interference when PSSK(Phase Silence Shift Keying) technique is applied to the low power underwater acoustic communication. PSSK is a QPSK(Quadrature Phase Shift Keying) modulation combined with PPM(Pulse Position Modulation), and it was proposed for low power communication. However, it has poor performance due to delay spread of underwater channel. In this paper, we propose a decision feedback equalizer to minimize the error in PSSK receiver. The sea trial was performed to evaluate the performance of the proposed method. In the result, the BER of PSSK was $4.36{\times}10^{-2}$ before the equalizer was applied, but the BER of PSSK was $3.95{\times}10^{-4}$ after the proposed equalizer was applied.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.53-58
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• 2020

This paper is concerned with the performance analysis of MSAGF-MMA with variable step size whose step size varies according to input power signal and decision-directed error signal. The proposed algorithm is made to change according to the input power signal which can reliably increase the convergence speed to the steady state by making the step size less affected by the fluctuation of the input signal in the MMA having the binary flag obtained from the modified Stop-and-Go algorithm. At the same time, the step size can be varied according to the decision-directed error signal so that the residual error can be reduced in the steady state. As a result of computer simulations, it is confirmed that the proposed algorithm has a very good performance in the evaluation of residual ISI and averaged-MSE in steady state as well as in terms of convergence speed to steady state compared to MMA and MSAGF-MMA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.93-96
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• 2005

We propose a computationally efficient sphere decoding (SD) algorithm with smart radius control (SRC). As a baseline algorithm for SD, we consider the modified Schnorr-Euchner (SE) algorithm [1] (hereafter, called as the MSE algorithm). In principle, the radius after zero-forcing decision feedback equalization (ZF-DFE) estimation can be reduced further if we select a new lattice vector closer to the received signal vector than the lattice vector corresponding to the ZF-DFE estimate does. In our case, we obtain such a better lattice vector by performing a sequence of alternating one-dimensional searches, starting from the ZF-DFE estimate. We then develop a novel SRC algorithm that adopts adaptively the additional radius reduction process according to the estimated signal-to-noise-power ratio (SNR) after ZF-DFE estimation. In addition, we analyze the effect of detection ordering on the complexity for SD. Column-norm ordering of the channel matrix and optimal ordering [1] are considered here. From our analyses, we see that SRC can reduce greatly the complexity for SD and the degree of complexity reduction gets significant as the SNR decreases, irrespective of detection ordering schemes used.