• Nuclear Engineering and Technology
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• v.42 no.2
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• pp.219-230
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• 2010

In nuclear power plants (NPPs), periodic sensor calibrations are required to assure that sensors are operating correctly. By checking the sensor's operating status at every fuel outage, faulty sensors may remain undetected for periods of up to 24 months. Moreover, typically, only a few faulty sensors are found to be calibrated. For the safe operation of NPP and the reduction of unnecessary calibration, on-line instrument calibration monitoring is needed. In this study, principal component-based auto-associative support vector regression (PCSVR) using response surface methodology (RSM) is proposed for the sensor signal validation of NPPs. This paper describes the design of a PCSVR-based sensor validation system for a power generation system. RSM is employed to determine the optimal values of SVR hyperparameters and is compared to the genetic algorithm (GA). The proposed PCSVR model is confirmed with the actual plant data of Kori Nuclear Power Plant Unit 3 and is compared with the Auto-Associative support vector regression (AASVR) and the auto-associative neural network (AANN) model. The auto-sensitivity of AASVR is improved by around six times by using a PCA, resulting in good detection of sensor drift. Compared to AANN, accuracy and cross-sensitivity are better while the auto-sensitivity is almost the same. Meanwhile, the proposed RSM for the optimization of the PCSVR algorithm performs even better in terms of accuracy, auto-sensitivity, and averaged maximum error, except in averaged RMS error, and this method is much more time efficient compared to the conventional GA method.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.101-110
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• 2006

One of the most effective ways to improve cache performance is to exploit both temporal and spatial locality given by any program executional characteristics. This paper proposes a data cache with small space for low power but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block sire and a fully-associative buffer with large block size. To overcome the disadvantage of small cache space, two mechanisms are enhanced by considering operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes and an efficient block filtering to remove rarely reused data. The simulations on MediaBench show that the proposed 5KB-cache can provide equivalent performance and reduce energy consumption up to 40% as compared with 16KB 4-way set associative cache.

• KEPCO Journal on Electric Power and Energy
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• v.4 no.2
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• pp.101-105
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• 2018

In this paper, the kernel regression model is applied for the case study of gas turbine abnormal state analysis. In addition to vibration analysis at the remote site, the kernel regression model technique can is useful for analyzing abnormal state of rotor vibration signals of gas turbine in power plant. In monitoring based on data-driven techniques correlated measurements, the fault free training data of shaft vibration obtained during normal operations of gas turbine are used to develop a empirical model based on auto-associative kernel regression. This data-driven model can be used to predict virtual measurements, which are compared with real-time data, generating residuals. Any faults in the system may cause statistically abnormal changes in these residuals and could be detected. As the result, the kernel regression model provides information that can distinguish anomalies such as sensor failure in a shaft vibration signal.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.4
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• pp.215-223
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• 2018

Recently, as interest of wearable devices has increased, commercially available smart wristbands and applications have been used as a tool for personal healthy management. However most previous studies have focused on evaluating the accuracy and reliability of the technical problems of wearable devices, especially step counts, walking distance, and energy consumption measured from the smart wristbands. In this study, we propose a physical activity evaluation model using classification rules, induced from the associative classification mining approach. These rules associated with five physical activities were generated by considering activities and walking times in target heart rate zones such as 'Out-of Zone', 'Fat Burn Zone', 'Cardio Zone', and 'Peak Zone'. In the experiment, we evaluated the prediction power of classification rules and verified its effectiveness by comparing classification accuracies between the proposed model and support vector machine.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.13 no.1
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• pp.40-47
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• 2017

In this paper, we investigate the feasibility of a strategy of failure detection and identification. The point of proposed strategy includes a pattern extraction approach for failure identification using Auto-Associative Kernel Regression (AAKR). We consider a simulation data concerning 605 signals of a Generic Pressurized Water Reactor(GPWR). In the application, the reconstructions are provided by a set of AAKR models, whose input signals have been selected by Correlation Analysis(CA) for the identification of the groups. The failure pattern is extracted by analyzing the residuals of observations and reconstructions. We present the possibility of extraction of patterns for six failure.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.232-243
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• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.289-292
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• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.2
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• pp.74-79
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• 2011

The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.1-8
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• 2011

NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way, victim and fully associative buffer with two or four sizes.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.69-78
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• 2009

One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.