• ETRI Journal
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• 제32권1호
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• pp.151-153
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• 2010

A highly efficient linear and compactly integrated series-type Doherty power amplifier (PA) has been developed for wideband code-division multiple access handset applications. To overcome the size limit of a typical Doherty amplifier, all circuit elements, such as matching circuits and impedance transformers, are fully integrated into a single monolithic microwave integrated circuit (MMIC). The implemented PA shows a very low idle current of 25 mA and an excellent power-added efficiency of 25.1% at an output power of 19 dBm by using an extended Doherty concept. Accordingly, its average current consumption was reduced by 51% and 41% in urban and suburban environments, respectively, when compared with a class-AB PA. By adding a simple predistorter to the PA, the PA showed an adjacent channel leakage ratio better than -42 dBc over the whole output power range.

• ETRI Journal
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• 제36권2호
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• pp.214-223
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• 2014

A fully-integrated penta-band reconfigurable power amplifier (PA) is developed for handset Tx applications. The output structure of the proposed PA is composed of the fixed output matching network, power and frequency reconfigurable networks, and post-PA distribution switches. In this work, a new reconfiguration technique is proposed for a specific band requiring power and frequency reconfiguration simultaneously. The design parameters for the proposed reconfiguration are newly derived and applied to the PA. To reduce the module size, the switches of reconfigurable output networks and post-PA switches are integrated into a single IC using a $0.18{\mu}m$ silicon-on-insulator CMOS process, and a compact size of $5mm{\times}5mm$ is thus achieved. The fabricated W-CDMA PA module shows adjacent channel leakage ratios better than -39 dBc up to the rated linear power and power-added efficiencies of higher than around 38% at the maximum linear output power over all the bands. Efficiency degradation is limited to 2.5% to 3% compared to the single-band reference PA.

• ETRI Journal
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• 제34권6호
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• 전기전자학회논문지
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• 제23권2호
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• pp.454-460
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• 2019

In this paper, a watt-level 2.4-GHz RFCMOS linear power amplifier (PA) with pre-distortion method using variable capacitance with respect to input power is demonstrated. The proposed structure is composed of a power detector and a MOS capacitor to improve the linearity of the PA. The pre-distortion based linearizer is embedded in the two-stage PA to compensate for the gain compression in the amplifier stages, it also improves the output P1dB by approximately 1 dB. The simulation results demonstrate a 1-dB gain compression power of 30.81 dBm at 2.4-GHz, and PAE is 29.24 % at the output P1dB point.

• 한국정보통신학회논문지
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• 제7권8호
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• pp.1612-1620
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• 2003

본 논문에서는 GaAsFET 전력증폭기를 다중반송 통신시스템에서 적용시키고자 설계한 PA증폭기의 측정된 전달함수를 비선형 모델링 한 결과를 제시하였으며 모델링 한 결과를 가지고 설계한 RF 증폭기의 AM­AM 및 AM­PM 비선형 특성을 추정하였다. 추정된 비선형특성 의하여 다중반송전송시스템에서의 증폭기의 근접채널간섭특성(ACPR), QPSK 및 64­QAM과 같은 디지털 변조 신호에 대하여 성상도에서의 데이터 오차벡터의 크기(EVM) 및 BER 관계를 분석하였다. 본 연구에서 제시한 RF GaAs FET의 비선형 모델링은 OFDM을 이용하는 무선 다중반송전송시스템 설계에 적용할 수 있으며 전력증폭기와 디지털 변조 신호에 따른 비선형 관계를 정확하게 추정할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.419-420
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• 2008

A power amplifier(PA) has been designed for 900 MHz-band applications. The PA consists of a single-ended CMOS amplifier which has $0.18{\mu}m{\times}64{\times}6$ gate width. The PA has been designed using $0.18{\mu}m$ CMOS process. At 900 MHz, the PA exhibit an output power of 20.8 dBm and a power-added efficiency(PAE) of 58.4 % with 22.2 dB power gain.

• Journal of electromagnetic engineering and science
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• 제15권2호
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• pp.63-75
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• 2015

The CMOS power amplifier (PA) is a promising solution for highly-integrated transmitters in a single chip. However, the implementation of PAs using the CMOS process is a major challenge because of the inferior characteristics of CMOS devices. This paper focuses on improvements to the efficiency and linearity of CMOS PAs for modern wireless communication systems incorporating high peak-to-average ratio signals. Additionally, an envelope tracking supply modulator is applied to the CMOS PA for further performance improvement. The first approach is enhancing the efficiency by waveform engineering. In the second approach, linearization using adaptive bias circuit and harmonic control for wideband signals is performed. In the third approach, a CMOS PA with dynamic auxiliary circuits is employed in an optimized envelope tracking (ET) operation. Using the proposed techniques, a fully integrated CMOS ET PA achieves competitive performance, suitable for employment in a real system.

• ETRI Journal
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• 제31권5호
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• pp.598-600
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• 2009

A highly efficient and compactly integrated balanced power amplifier (PA) for W-CDMA handset applications is presented. To overcome the size limit of a typical balanced PA, a bulky input divider is integrated into a PA MMIC, and a complex output network is replaced with simple lumped-element networks. For efficiency improvement at the low output power level, one of the two amplifiers in parallel is deactivated and the other is partially operated with corresponding load impedance optimization. The implemented PA shows excellent average current consumption of 34.5 mA in urban and 56.3 mA in suburban environments, while exhibiting very good load-insensitivity under condition of VSWR=4:1.