• Title/Summary/Keyword: power MOS

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A Parallel Resonant inverter linked type DC-DC Converter with active-c1amp circuits (능동클램프회로를 갖는 병렬공전 인버터 링크형 DC-DC 컨버터)

  • 오경섭;남승식;김동희;김희대;선우영호
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2003.11a
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    • pp.311-314
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    • 2003
  • In this paper, proposed circuit proposes that Active-Clamp-Circuits basis of a current-fed inverter linked type high frequency resonant dc-dc converter of conventional. and the paper the most of characteristics of the reduced high voltage stress main switches with active clamp circuits and output current constant with the resonant part consists of L, C resonant tank circuit. Also, the capacitor (C$_1$, C$_2$) connected in switches are a common using by resonance capacitor and ZVS capacitor. and circuit analysis used state equation of each part modes. Also we conform a rightfulness theoretical analysis by comparing a parameters values and simulation values obtained from simulation using Power MOS-FET as switching devices.

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Analysis for the parallel operation of IGBT considering snubber circuit (스너버를 고려한 IGBT의 병렬운전 특성해석)

  • Kim, Yoon-Ho;Yoon, Byung-Do;Lee, Jang-Sun;Lee, Sang-Sup
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.777-780
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    • 1993
  • An insulated gate bipolar transistor(IGBT) is a MOS gate turn on/off bipolar transistor which combines the attributes of the MOSFET and bipolar transistor. Because of its limitation of power capability compared to thyristor or GTO, some parallel connection of IGBT has been studied to improve the limitation of current capabillity. In this paper, the switching effects from the unbalance of internal parameters of IGBT and the turn-off snubber characteristics are investigated using SPICE program.

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Effect of R-C Compensation on Switching Regulation of CMOS Low Dropout Regulator

  • Choi, Ikguen;Jeong, Hyeim;Yu, Junho;Kim, Namsoo
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.3
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    • pp.172-177
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    • 2016
  • Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

development of Underwater Data Communication System (I) -Echo Signal Transfer System- (수중 데이터 통신 시스템의 개발에 관한 연구 (I) -에코 신호 전송 시스템-)

  • 신현옥
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.35 no.3
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    • pp.284-290
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    • 1999
  • This paper describes a Frequency Shift Keying (FSK) modulator and demodulator and the experimented underwater data ommunication equipment to transfer the analog echo signal in real-time from an underwater vehicle to the mother ship. The system consists of an echo signal transfer unit equipped to the vehicle and an ultrasonic receiver equipped on the ship. The former includes an ultrasonic transceiver unit of 180kHz for echo detection and a continuous wave transmitter of 50kHz with a FSK modulator for echo transmission to the ship. The latter includes an ultrasonic receiver of 50kHz and the FSK demodulator. The results of experiment are as follows. 1. The characteristics of the FSK modulating and demodulating circuits designed with the use of C-MOS IC 4046 was good and confirmed its usefulness in underwater data communication system.2. The prototype ultrasonic transceiver unit shows profitable driving power while the pulse duration was short less than 3 msec, but it was found that the driving power is not sufficient while the long pulse duration or continuous wave is used. The gain of the ultrasonic receiver was 80 dB and the receiving bandwidth 700Hz (at - 3 dB point).3. It was found that the system designed by the author has some possibility to use in underwater echo transfer.4. At the FSK modulator, the widths of voltage and frequency which represent linearity were 3.5 V, 1600Hz, respectively, at the FSK demodulator 2.6 V, 700Hz, respectively.

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development of Underwater Data Communication System (I) -Echo Signal Transfer System- (수중 데이터 통신 시스템의 개발에 관한 연구 (I) -에코 신호 전송 시스템-)

  • 신현옥
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.35 no.3
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    • pp.285-285
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    • 1999
  • This paper describes a Frequency Shift Keying (FSK) modulator and demodulator and the experimented underwater data ommunication equipment to transfer the analog echo signal in real-time from an underwater vehicle to the mother ship. The system consists of an echo signal transfer unit equipped to the vehicle and an ultrasonic receiver equipped on the ship. The former includes an ultrasonic transceiver unit of 180kHz for echo detection and a continuous wave transmitter of 50kHz with a FSK modulator for echo transmission to the ship. The latter includes an ultrasonic receiver of 50kHz and the FSK demodulator. The results of experiment are as follows. 1. The characteristics of the FSK modulating and demodulating circuits designed with the use of C-MOS IC 4046 was good and confirmed its usefulness in underwater data communication system.2. The prototype ultrasonic transceiver unit shows profitable driving power while the pulse duration was short less than 3 msec, but it was found that the driving power is not sufficient while the long pulse duration or continuous wave is used. The gain of the ultrasonic receiver was 80 dB and the receiving bandwidth 700Hz (at - 3 dB point).3. It was found that the system designed by the author has some possibility to use in underwater echo transfer.4. At the FSK modulator, the widths of voltage and frequency which represent linearity were 3.5 V, 1600Hz, respectively, at the FSK demodulator 2.6 V, 700Hz, respectively.

Current Sensing Circuit of MOSFET Switch for Boost Converter (부스터 변환기를 위한 MOSFET 스위치 전류 감지 회로)

  • Min, Jun-Sik;No, Bo-Mi;Kim, Eui-Jin;Lee, Chan-Soo;Kim, Yeong-Seuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.9
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    • pp.667-670
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    • 2010
  • In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

A Design of High-Speed Level-Shifter using Reduced Swing and Low-Vt High-Voltage Devices (Reduced Swing 방식과 Low-Vt 고전압 소자를 이용한 고속 레벨시프터 설계)

  • Seo, Hae-Jun;Kim, Young-Woon;Ryu, Gi-Ju;Ahn, Jong-Bok;Cho, Tae-Won
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.525-526
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    • 2008
  • This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

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On the detection of faults on digital logic circuits using current sensor (전류 센서를 이용한 디지탈 논리회로의 고장 검출)

  • 신재흥;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.2
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    • pp.173-183
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    • 1996
  • In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

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Design of 3V a Low-Power CMOS Analog-to-Digital Converter (3V 저전력 CMOS 아날로그-디지털 변환기 설계)

  • 조성익;최경진;신홍규
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.10-17
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    • 1999
  • In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

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Electrical Characteristic of Power MOSFET with Zener Diode for Battery Protection IC

  • Kim, Ju-Yeon;Park, Seung-Uk;Kim, Nam-Soo;Park, Jung-Woong;Lee, Kie-Yong;Lee, Hyung-Gyoo
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.1
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    • pp.47-51
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    • 2013
  • A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.