• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1075-1078
• /
• 2007

Negative Bias Temperature Instability (NBTI) in Eximer Laser Annealing (ELA) based Low Temperature polysilicon (LTPS) Thin-Film Transistors (TFT) was investigated. Even though NBTI is generally appeared in devices with thin gate oxide, the TFT with gate oxide thickness of 120 nm, relatively thick, also showed NBTI effect and dynamic NBTI effect is dependent on operational frequency.

• Proceedings of the Korean Institute of Building Construction Conference
• /
• 2017.05a
• /
• pp.173-174
• /
• 2017

Recently, many experiments using industrial by-products have been going on in Korea and abroad. Most of the studies on blast furnace slag and fly ash have been conducted, and the blast furnace slag based two and three component experiments have been conducted in many places. Therefore, this study is an additional study of research using polysilicon sludge and paper ash, which is a study using existing industrial by-products based on blast furnace slag, as strength properties of alkali activator according to kind and mixing ratio and to obtain basic data do.

• Proceedings of the Korean Institute of Building Construction Conference
• /
• 2016.05a
• /
• pp.132-133
• /
• 2016

The Present that environmentally friendly policies at issue in the world recently, construction sector and other sectors are working on reducing CO₂. Cement production during in the construction sector, CO₂ is being caused in large quantities. Therefore, this study was secure the basic date that not use cement and use blast furnace slag and fly ash HFA, polysilicon in industrial byproducts about cement non-cement matrix.

• Proceedings of the KIEE Conference
• /
• 1987.07a
• /
• pp.416-419
• /
• 1987

The miniaturization of Bird's Beak generated at the field oxidation has been studied by adding polysilicon layer between the silicon nitride and pad oxide stack, which is the basic structure of Conventional LOCOS. The size and shape of Bird's Beak were intensively observed by SEM, and also the electrical characteristics of Bird's Beak-reduced LOCOS structure were compared with those of Conventional LOCOS. The length of Bird's Beak was reached up to $0.20-0.28{\mu}m$, while about to $0.50-0.53{\mu}m$ in conventional LOCOS, resulting in 60% reduction.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.6
• /
• pp.795-800
• /
• 1986

High value sheet resistance (Rs, 350\ulcorner/ -80K\ulcorner/) born implanted polysilicon resistors were fabricated under process conditions compatible with bipolar integrated circuits fabrications. This paper includes studies of sensitivity of Rs to doping concentration, the effect of thermal annealing temperature on Rs, temperature coefficient of resistance (TCR), the effect of polysilicon thickness on Rs and the Rs variation within a run and between runs.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.1
• /
• pp.16-22
• /
• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.5 no.4
• /
• pp.367-370
• /
• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1050-1053
• /
• 2002

In this paper, Amorphous silicon on glass substrate was recrystallized to poly-crystalline silicon by solid phase crystallization (SPC) technology. The active region of thin film transistor (TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain (LDD) structure was measured and analyzed. As a results, analyzed TFTs reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.185-188
• /
• 2002

In this paper, Amorphous silicon on glass substrate was recrytallized to poly-crystalline silicon by solid phase crystallization(SPC) technology The active region of thin film transistor(TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain(LDD) structure was measured and analyzed. As a results, analyzed TFT's reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.10a
• /
• pp.634-639
• /
• 2001

In this paper, we discuss optimum process conditions of Hemispherical Grained Silicon formation for high density DRAM'S capacitor. In optimum process renditions, the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 40(equation omitted), respectively. in the 64M bit DRAM capacitor using optimum process conditions, limit thickness of nitride is about 65(equation omitted). The results obtained in this study are applicable to process control and HSG-Si formation for high reliability and high density DRAM's capacitor.