• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.261-264
• /
• 2007

We developed a non self-aligned poly-silicon TFTs fabrication process at two different temperatures on spin-coated polyimide layer above Si-wafer. After TFTs fabrication, the polyimide layer was mechanically released from the Si-wafer and the devices characteristics were compared. In addition self-heating and hot-carrier induced instabilities were analysed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.1
• /
• pp.99-102
• /
• 2002

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are found and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8${\mu}{\textrm}{m}$ thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point makes the gate oxide broken. 1'he arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if are occurrence points are found on scribeline.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1993.11a
• /
• pp.64-66
• /
• 1993

The charateristics of low temperature poly-Si thin films with different growth condition were investigated and poly-Si TFTs were fabricated on solid phase crystallized (SPC) amorphous silicon films and as-deposited poly-Si films. The performance of devices fabricated on the SPC amorphous silicon films was shown to be superior to that of devices fabricated on as-deposited poly-Si films. It was found that the characteristics of low-temperature poly-Si thin films such as surface roughness, crystal texture and grain size strongly influenced the poly-Si TFT performance.

• Journal of the Korean institute of surface engineering
• /
• v.27 no.2
• /
• pp.83-90
• /
• 1994

We have investigated the mechanism for the abnormal oxide growth occuring during oxidation of the crystalline tungsten silicide. TEM and XPS analysis reveal the abnormaly grown oxide layer consisting of crystalline $Wo_3$ and amorphous $SiO_2$. The presence of crystalline $Wo_3$ provides a rapid diffusion of oxygen through the oxide layer. The abnormal oxide growth is mainly due to the poor quality of initial oxide layer growth on tungsten silicide. Two species such as tungsten and silicon from decomposition fo tungsten silicide as well as silicon supplied from the underlying polysilicon are the main contributors sto abnormal oxide forma-tion. Consequently, the abnormal oxidation results in the disintegration of tungsten silicide and thinning of polysilicon as well.

• Korean Journal of Materials Research
• /
• v.4 no.7
• /
• pp.750-758
• /
• 1994

The purpose of present study is to find out the formation mechanism of hemi-spherical grained(HSG) polysilicon film. Silicon film was deposited using LPCVD. Polycrystalline silicon film was deposited at $575^{\circ}C$ contained crystalline HSG in the amorphous matrix phase. The crystalline HSG can be categorized into two grains : lower grains and upper grains. Lower grains are located at interface between silicon dioxide and silicon film, and upper grains are located at surface. The growth orientations of HSG were identified as (311) or (111) directions for lower grains and perferentially (110) direction for upper grains. This difference of growth orientations seems to be caused by the difference of formation mechanisms. That is, lower grain is formed by soild phase crystallization, on the other hand, upper grain is formed by surface diffusion of silicon atoms. It was thus, proposed that the formation of practical HSG polysilicon film is mainly controlled by surface diffusion of silicon atoms.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.18 no.4
• /
• pp.137-139
• /
• 2008

Floating zone, neutron transmutation-doped and magnetic Czochralski silicon crystals are being widely used for fabrication power devices. To improve the quality of these devices and to decrease their production cost, it is necessary to use large-diameter wafers with high and uniform resistivity. Recent developments in the crystal growth technology of Czochralski silicon have enable to produce Czochralski silicon wafers with sufficient resistivity and with well-controlled, suitable concentration of oxygen. In addition, using Czoehralski silicon for substrate materials may offer economical benefits, First, Czoehralski silicon wafers might be cheaper than standard floating zone silicon wafers, Second, Czoehralski wafers are available up to diameter of 300 mm. Thus, very large area devices could be manufactured, which would entail significant saving in the costs, In this work, the conventional Czochralski silicon crystals were grown with higher oxygen concentrations using high pure polysilicon crystals. The silicon wafers were annealed by several steps in order to obtain saturated oxygen precipitation. In those wafers high resistivity over $5,000{\Omega}$ cm is kept even after thermal donor formation annealing.

• Journal of the Korean Vacuum Society
• /
• v.7 no.3
• /
• pp.169-175
• /
• 1998

The plasma etching of polysilicon was performed with the HBr/$Cl_2/He-O_2$ gas mixture. The residual layers after photoresist strip were investigated using x-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). The etch residue was identified as silicon oxide deposited on the top of the patterned polysilicon. In order to clarify the formation mechanism of the etch residue, the effects of various gas mixtures such as $Cl_2/He-O_2$and HBr/$Cl_2$were investigated. We found that the etch residue is well formed in the presence of oxygen, suggesting that the etch residue is caused by the reaction of oxvgen and non-volatile silicon halide compounds. Wet cleaning and dry etch cleaning processes were applied to remove the polysilicon etch residue, which can affect the electrical characteristics and further device processes. XPS results show that the wet cleaning is suitable for the removal of the etch residue.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.34 no.4
• /
• pp.391-398
• /
• 2010

In this paper, we propose a sensor design by using a polysilicon strain gauge bonded to a metal diaphragm. The fabrication process of the thin polysilicon strain gauges having thicknesses of $50\;{\mu}m$ was established using conventional MEMS technologies; further, the technique of glass frit bonding of the polysilicon strain gauge to the stainless steel diaphragm was established. Performance of the polysilicon strain gauge bonded to the metal cantilever beam was evaluated. The gauge factor, temperature coefficient of resistance (TCR), nonlinearity, and hysteresis of the polysilicon strain gauge were measured. The results demonstrate that the resistance increases linearly with tensile stress, while it decreases with compressive stress. The value of the gauge factor, which represents the sensitivity of strain gauges, is 34.0; this value is about 7.15 times higher than the gauge factor of a metal-foil strain gauge. The resistance of the polysilicon strain gauge decreases linearly with an increase in the temperature, and TCR is $-328\;ppm/^{\circ}C$. Further, nonlinearity and hysteresis are 0.21 % FS and 0.17 % FS, respectively.

• Proceedings of the KIEE Conference
• /
• 1998.07g
• /
• pp.2518-2520
• /
• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.20 no.5
• /
• pp.1363-1371
• /
• 1996

This paper presents the design, fabrication, and testing of polysilicon electrostatic microactuators that resonate in the direction parallel to the silicon susbstrates. A set of six different designs has been developed using a theoretical model and design formulae developed for the mocroactuators. Microactuator prototypes are fabricated from a 2.1 $\mu{m}$-thick LPCVD polysilicon film, using a 4-mask surface-micromachining process. The prototypes are tested under a d.c. bias voltage of 45V with an a.c. drive voltage amplitude of 20 v.Measured resorant frequencies are in the ranges of 40-60 kHz, showing a good agreement to their theoretical estimates within error bounds of .$\pm$.5%. Important issues inthe design and microfabrication of the microactuators are discussed, together with potential applicaitons of the key technology involved.