• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.173-176
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• 2004

In this study we investigated post ELA(Excimer Laser Annealing) effect on SMC (Silicide Mediated Crystalization) poly-Si (Polycrystalline Silicon) to improve the characteristics of poly-Si. Combining SMC and XeCl ELA were used to crystallize the a-Si (amorphous Silicon) at various ELA energy density for LTPS (Low Temperature Polycrystalline Silicon). We fabricated the conventional SMC poly-Si with no SPC (Solid Phase Crystallization) phase using UV heating method[1] and irradiated excimer laser on SMC poly-Si, so called SMC-ELA poly-Si. After using post ELA we can get better surface morphology than conventional ELA poly-Si and enhance characteristics of SMC poly-Si. We also observed the threshold energy density regime in SMC-ELA poly-Si like conventional ELA poly-Si.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.724-728
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• 2002

Inductively-coupled $N_2$O plasma was utilized to grow silicon dioxide at low temperature and applied to fabricate polycrystalline-silicon thin film transistors. At $400^{\circ}C$, the thickness of oxide was limited to 5nm and the oxide contained Si≡N and ≡Si-N-Si≡ bonds. The nitrogen incorporation improved breakdown field to 10MV/cm and reduced the interface charge density to $1.52$\times$10^{11}$ $cm^2$ with negative charge. The $N_2$O plasma gate oxide enhanced the field effect mobility of polycrystalline thin film transistor, compared to $O_2$ plasma gate oxide, due to the reduced interface charge at the $Si/SiO_2$ interface and also due to the reduced trap density at Si grain boundaries by nitrogen passivation.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.225-229
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• 2002

LPCVD silicon films were deposited at temperatures between $560^{\circ}C$ and $650^{\circ}C$ Structure, surface roughness, films thickness and residual stress were measured by using XRD, SEM, ellipsometer, $Tektak^3$, Tencor FLX-2320 and other techniques. Polysilicon films of low stress, small surface roughness were obtained when the films are deposited at $560^{\circ}C$ in the amorphous phase and subsequently annealed to make polycrystalline silicon layers at $900^{\circ}C$ -$1100^{\circ}C$. The silicon films deposited in amorphous phase and crystallized by post thermal treatment showed better mechanical properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.78-81
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• 1994

The Photovoltaics(PV) industry has been evolving over the last 30 years and expanding because of a rising demand for clean and safe energy. Crystalline silicon solar cells will have increased performance and reduced cost in the future. In this paper solution growth process used to fabricate polycrystalline silicon thin film is considered.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.459-462
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• 2007

An electric field was applied to a conductive layer to induce Joule heating in order to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced through a solid state transformation within the range of a millisecond. Uniformly distributed grains were obtained due to enormously high heating rate.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.75.2-75.2
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• 2010

We studied the fabrication of polycrystalline silicon (pc-Si) films as seed layers for application of pc-Si thin film solar cells, in which amorphous silicon (a-Si) films in a structure of glass/Al/$Al_2O_3$/a-Si are crystallized by the aluminum-induced layer exchange (ALILE) process. The properties of pc-Si films formed by the ALILE process are strongly determined by the oxide layer as well as the various process parameters like annealing temperature, time, etc. In this study, the effects of the oxide film thickness on the crystallization of a-Si in the ALILE process, where the thickness of $Al_2O_3$ layer was varied from 4 to 50 nm. For preparation of the experimental film structure, aluminum (~300 nm thickness) and a-Si (~300 nm thickness) layers were deposited using DC sputtering and PECVD method, respectively, and $Al_2O_3$ layer with the various thicknesses by RF sputtering. The crystallization of a-Si was then carried out by the thermal annealing process using a furnace with the in-situ microscope. The characteristics of the produced pc-Si films were analyzed by optical microscope (OM), scanning electron microscope (SEM), Raman spectrometer, and X-ray diffractometer (XRD). As results, the crystallinity was exponentially decayed with the increase of $Al_2O_3$ thickness and the grain size showed the similar tendency. The maximum pc-Si grain size fabricated by ALILE process was about $45{\mu}m$ at the $Al_2O_3$ layer thickness of 4 nm. The preferential crystal orientation was <111> and more dominant with the thinner $Al_2O_3$ layer. In summary, we obtained a pc-Si film not only with ${\sim}45{\mu}m$ grain size but also with the crystallinity of about 75% at 4 nm $Al_2O_3$ layer thickness by ALILE process with the structure of a glass/Al/$Al_2O_3$/a-Si.

• Korean Journal of Materials Research
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• v.5 no.2
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• pp.197-202
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• 1995

The surface morphology and grain growth of amophous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD) have been investigated as a function of deposition and in sltu annealing condition. The film deposited at the amorphous to polycrystalline transition temperature has an extra-rough, rugged surface with (311) t.exture. At the same deposition temperature, the grain structure tends to shirr. from the polycrystalline to the amorphous phase with increasing the film thickness. It is found that nucleation of a-Si during in situ annealing at the transition temperature without breaking the vacuum starts to occur from surface Si atom migration in contrast to a heterogeneous nucleation during film deposition.

• Korean Journal of Materials Research
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• v.4 no.7
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• pp.750-758
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• 1994

The purpose of present study is to find out the formation mechanism of hemi-spherical grained(HSG) polysilicon film. Silicon film was deposited using LPCVD. Polycrystalline silicon film was deposited at $575^{\circ}C$ contained crystalline HSG in the amorphous matrix phase. The crystalline HSG can be categorized into two grains : lower grains and upper grains. Lower grains are located at interface between silicon dioxide and silicon film, and upper grains are located at surface. The growth orientations of HSG were identified as (311) or (111) directions for lower grains and perferentially (110) direction for upper grains. This difference of growth orientations seems to be caused by the difference of formation mechanisms. That is, lower grain is formed by soild phase crystallization, on the other hand, upper grain is formed by surface diffusion of silicon atoms. It was thus, proposed that the formation of practical HSG polysilicon film is mainly controlled by surface diffusion of silicon atoms.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.4
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• pp.181-184
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• 2004

Thin films of single phase, polycrystalline silicon germanium (Si$_{1-x}$ Ge$_{x}$) were prepared by ion-beam evaporation (IBE) using Si-Ge multi-phase targets. After irradiation of the targets by a pulsed light ion beam with peak energy of 1 MV, 450 and 480 nm thick films were deposited on Si single crystal and quartz glass substrates, respectively. From XRD analysis, the thin films consisted of a single phase Si$_{1-x}$ Ge$_{x}$, whose composition is close to those of the targets.rgets.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.