• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1261-1262
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• 2008

Laser-based crystallization techniques are ideally-suited for forming high-quality crystalline Si films on active-matrix display backplanes, because the highly-localized energy deposition allows for transformation of the as-deposited a-Si without damaging high-temperature-intolerant glass and plastic substrates. However, certain significant and non-trivial attributes must be satisfied for a particular method and implementation to be considered manufacturing-worthy. The crystallization process step must yield a Si microstructure that permits fabrication of thin-film transistors with sufficient uniformity and performance for the intended application and, the realization and implementation of the method must meet specific requirements of viability, robustness and economy in order to be accepted in mass production environments. In recent years, Low Temperature Polycrystalline Silicon (LTPS) has demonstrated its advantages through successful implementation in the application spaces that include highly-integrated active-matrix liquid-crystal displays (AMLCDs), cost competitive AMLCDs, and most recently, active-matrix organic light-emitting diode displays (AMOLEDs). In the mobile display market segment, LTPS continues to gain market share, as consumers demand mobile devices with higher display performance, longer battery life and reduced form factor. LTPS-based mobile displays have clearly demonstrated significant advantages in this regard. While the benefits of LTPS for mobile phones are well recognized, other mobile electronic applications such as portable multimedia players, tablet computers, ultra-mobile personal computers and notebook computers also stand to benefit from the performance and potential cost advantages offered by LTPS. Recently, significant efforts have been made to enable robust and cost-effective LTPS backplane manufacturing for AMOLED displays. The majority of the technical focus has been placed on ensuring the formation of extremely uniform poly-Si films. Although current commercially available AMOLED displays are aimed primarily at mobile applications, it is expected that continued development of the technology will soon lead to larger display sizes. Since LTPS backplanes are essentially required for AMOLED displays, LTPS manufacturing technology must be ready to scale the high degree of uniformity beyond the small and medium displays sizes. It is imperative for the manufacturers of LTPS crystallization equipment to ensure that the widespread adoption of the technology is not hindered by limitations of performance, uniformity or display size. In our presentation, we plan to present the state of the art in light sources and beam delivery systems used in high-volume manufacturing laser crystallization equipment. We will show that excimer-laser-based crystallization technologies are currently meeting the stringent requirements of AMOLED display fabrication, and are well positioned to meet the future demands for manufacturing these displays as well.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.53.2-53.2
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• 2010

지금까지 능동 구동 디스플레이의 TFT backplane에 사용하고 있는 채널 물질로는 수소화된 비정질 실리콘(a-Si:H)과 저온 폴리실리콘(low temperature poly-Si)이 대표적이다. 수소화된 비정질 실리콘은 TFT-LCD 제조에 주로 사용되는 물질로 제조 공정이 비교적 간단하고 안정적이며, 생산 비용이 낮고, 소자 간 특성이 균일하여 대면적 디스플레이 제조에 유리하다. 그러나 a-Si:H TFT의 이동도(mobility)가 1 cm2/Vs이하로 낮아 Full HD 이상의 대화면, 고해상도, 고속 동작을 요구하는 UD(ultra definition)급 디스플레이를 개발하는데 있어 한계 상황에 다다르고 있다. 또한 광 누설 전류(photo leakage current)의 발생을 억제하기 위해서 화소의 개구율(aperture ratio)을 감소시켜야하므로 패널의 투과율이 저하되고, 게이트 전극에 지속적으로 바이어스를 인가 시 TFT의 문턱전압(threshold voltage)이 열화되는 문제점을 가지고 있다. 문제점을 극복하기 위한 대안으로 근래 투명 산화물 반도체(transparent oxide semiconductor)가 많은 관심을 얻고 있다. 투명 산화물 반도체는 3 eV 이상의 높은 밴드갭(band-gap)을 가지고 있어 광 흡수도가 낮아 투명하고, 광 누설 전류의 영향이 작아 화소 설계시 유리하다. 최근 다양한 조성의 산화물 반도체들이 TFT 채널 층으로의 적용을 목적으로 활발하게 연구되고 있으며 ZnO, SnO2, In2O3, IGO(indium-gallium oxide), a-ZTO(amorphous zinc-tin-oxide), a-IZO (amorphous indium-zinc oxide), a-IGZO(amorphous indium-galliumzinc oxide) 등이 그 예이다. 이들은 상온 또는 $200^{\circ}C$ 이하의 낮은 온도에서 PLD(pulsed laser deposition)나 스퍼터링(sputtering)과 같은 물리적 기상 증착법(physical vapor deposition)으로 손쉽게 증착이 가능하다. 특히 이중에서도 a-IGZO는 비정질임에도 불구하고 이동도가 $10\;cm2/V{\cdot}s$ 정도로 a-Si:H에 비해 월등히 높은 이동도를 나타낸다. 이와 같이 a-IGZO는 비정질이 가지는 균일한 특성과 양호한 이동도로 인하여 대화면, 고속, 고화질의 평판 디스플레이용 TFT 제작에 적합하고, 뿐만 아니라 공정 온도가 낮은 장점으로 인해 플렉시블 디스플레이(flexible display)의 backplane 소재로서도 연구되고 있다. 본 실험에서는 rf sputtering을 이용하여 증착한 a-IGZO 박막에 대하여 열처리 조건 변화에 따른 a-IGZO 박막들의 광학적, 전기적 특성변화를 살펴보았고, 이와 더불어 a-IGZO 박막을 TFT에 적용하여 소자의 특성을 분석함으로써, 열처리에 따른 Transfer Curve에서의 우리가 요구하는 Threshold Voltage(Vth)의 변화를 관찰하였다.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1352-1354
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• 1998

$LiNbO_3$ transistor showed relatively stable characteristic, low interface trap density, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$ thin films grown directly on p-type Si(100) substrates by 13.56 MHz rf magnetron sputtering system for FRAM applications. To take advantage of low temperature requirement for growing films, we deposited $LiNbO_3$ films lower than $300 ^{\circ}C$. RTA(Rapid Thermal Anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60 sec. We learned from X-ray diffraction that the RTA annealed films were changed from amorphous to poly-crystalline $LiNbO_3$ which exhibited (012), (015), and (022) orientations. The I-V characteristics of $LiNbO_3$ films before and after anneal treatment showed that RTA improved the leakage current of films. The leakage current density of films decreased from $10^{-5}$ to $10^{-7} A/cm^2$ at room temperature measurement. Breakdown electric field of the films exhibited higher than 500 kV/cm. The C-V curves showed the clockwise hysteresis represents ferroelectric switching characteristics. From C-V curves, we calculated dielectric constant of thin film $LiNbO_3$ as 27.5 which is close to that of bulk value.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.31-37
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• 2000

In the case of metal-induced lateral crystallization (MILC) for low temperature poly-Si TFT, offset length between Ni-thin film and the sides of gate could be modified to control the location of MILC boundary. Electrical characteristics were compared to analyze the effect of MILC boundary that was located either in or out of the channel region of the TFT. By removing the MILC boundary from channel region, on current, subthreshold slope and leakage current properties could be improved. When MILC boundary was located in the channel region, leakage current was reduced with electrical stress biasing. The amount of reduction increased as the channel width increased, but it was independent of the channel length.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.110-110
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• 2010

현재 박막 트랜지스터는 비정질 실리콘 기반의 개발이 주를 이루고 있으며, 이 비정질 실리콘은 성막공정이 간단하고 대면적에 용이하지만 전기적인 특성이 우수하지 않기 때문에 디스플레이의 적용에 어려움을 겪고 있다. 이에 따라 poly-Si을 이용한 박막 트랜지스터의 연구가 진행되고 있는데, 이는 공정온도가 높고, 대면적에의 응용이 어렵다. 따라서 앞으로 저온 공정이 가능하며 대면적 응용이 용이한 박막 트랜지스터의 연구가 필수적이다. 한편 최근 박막 트랜지스터의 채널층으로 사용되는 물질에는 oxide 기반의 ZnO, SnO2, In2O3 등이 주로 사용되고 있고, 보다 적합한 채널층을 찾기 위한 연구가 많이 진행되어 왔다. 최근 Hosono 연구팀에서 IGZO를 채널층으로 사용하여 high mobility, 우수한 on/off ratio의 특성을 가진 소자 제작에 성공함으로써 이를 시작으로 IGZO의 연구 또한 세계적으로 활발한 연구가 이루어지고 있다. 특히, ZnO는 wide band gap (3.37eV)을 가지고 있어 적외선 및 가시광선의 투과율이 좋고, 전기 전도성과 플라즈마에 대한 내구성이 우수하며, 낮은 온도에서도 성막이 가능하다는 특징을 가지고 있다. 그러나 intrinsic ZnO 박막은 bias stress 같은 외부 환경이 변했을 경우 전기적인 성질의 변화를 가져올 뿐만 아니라 고온에서의 공정이 불안정하다는 요인을 가지고 있다. ZnO의 전기적인 특성을 개선하기 위해 본 연구에서는 hafnium을 doping한 ZnO을 channel layer로 소자를 제작하고 전기적 특성을 평가하였다. 이를 위해 DC magnetron sputtering을 이용하여 ZnO 기반의 박막 트랜지스터를 제작하였다. Staggered bottom gate 구조로 ITO 물질을 전극으로 사용하였으며, 제작된 소자는 semiconductor analyzer를 이용하여 출력특성과 전이 특성을 평가하였으며, ZnO channel layer 증착시 hafnium이 도핑 되는 양을 조절하여 소자를 제작한 후 intrinsic ZnO의 소자 특성과 비교 분석하였다. 그 결과 hafnium을 doping 시킨 소자의 field effect mobility가 $6.42cm^2/Vs$에서 $3.59cm^2/Vs$로 낮아졌지만, subthreshold swing 측면에서는 1.464V/decade에서 0.581V/decade로 intrinsic ZnO 보다 좋은 특성을 나타냄을 알 수 있었다. 그리고 intrinsic ZnO의 경우 외부환경에 대한 안정성 문제가 대두되고 있는데, hafnium을 도핑한 ZnO의 경우 temperature, bias temperature stability, 경시변화 등의 다양한 조건에서의 안정성이 확보된다면 intrinsic ZnO 박막트랜지스터의 문제점을 해결할 수 있는 물질로 될 것이라고 기대된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.659-659
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• 2013

Recently, graphene has been intensively studied due to the fascinating physical, chemical and electrical properties. It shows high carrier mobility, high current density, and high thermal conductivity compare with conventional semiconductor materials even it has single atomic thickness. Especially, since graphene has fantastic electrical properties many researchers are believed that graphene will be replacing Si based technology. In order to realize it, we need to prepare the large and uniform graphene. Chemical vapor deposition (CVD) method is the most promising technique for synthesizing large and uniform graphene. Unfortunately, CVD method requires transfer process from metal catalyst. In transfer process, supporting polymer film (Such as poly (methyl methacrylate)) is widely used for protecting graphene. After transfer process, polymer layer is removed by organic solvents. However, it is impossible to remove it completely. These organic residues on graphene surface induce quality degradation of graphene since it disturbs movement of electrons. Thus, in order to get an intrinsic property of graphene completely remove of the organic residues is the most important. Here, we introduce modified wet graphene transfer method without PMMA. First of all, we grow the graphene from Cu foil using CVD method. And then, we deposited several metal films on graphene for transfer layer instead of PMMA. Finally, we fabricate graphene FET devices. Our approaches show low defect density and non-organic residues in comparison with PMMA coated graphene through Raman spectroscopy, SEM and AFM. In addition, clean graphene FET shows intrinsic electrical characteristic and high carrier mobility.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.117-117
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• 2008

In MIM capacitor, poly-Si bottom electrode is replaced with metal bottom electrode. Noble metals can be used as bottom electrodes of capacitors because they have high work function and remain conductive in highly oxidizing conditions. In addition, they are chemically very stable. Among novel metals, Ru (ruthenium) has been suggested as an alternative bottom electrode due to its excellent electrical performance, including a low leakage of current and compatibility to high dielectric constant materials. Chemical mechanical planarization (CMP) process has been suggested to planarize and isolate the bottom electrode. Even though there is a great need for development of Ru CMP slurry, few studies have been carried out due to noble properties of Ru against chemicals. In the organic chemistry literature, periodate ion ($IO_4^-$) is a well-known oxidant. It has been reported that sodium periodate ($NaIO_4$) can form $RuO_4$ from hydrated ruthenic oxide ($RuO_2{\cdot}nH_2O$). $NaIO_4$ exist as various species in an aqueous solution as a function of pH. Also, the removal mechanism of Ru depends on solution of pH. In this research, the static etch rate, passivation film thickness and wettability were measured as a function of slurry pH. The electrochemical analysis was investigated as a function of pH. To evaluate the effect of pH on polishing behavior, removal rate was investigated as a function of pH by using patterned and unpatterned wafers.

• Advances in Energy Research
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• v.1 no.2
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• pp.97-106
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• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.33-36
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• 2009

Inorganic-organic composite thin-film-transistors (TFTs) of ZnO nanowire/Poly(3-hexylthiophene) (P3HT) were investigated by changing the nanowire densities inside the composites. Crystalline ZnO nanowires were synthesized via an aqueous solution method at a low temperature, and the nanowire densities inside the composites were controlled by changing the ultrasonifiaction time. The channel layers were prepared with composites by spin-coating at 2000 rpm, which was followed by annealing in a vacuum at $100^{\circ}C$ for 10 hours. Au/inorganic-organic composite layer/$SiO_2$ structures were fabricated and the mobility, $I_{on}/I_{off}$ ratio, and threshold voltage were then measured to analyze the electrical characteristics of the channel layer. Compared with a P3HT TFT, the electrical properties of TFT were found to be improved after increasing the nanowire density inside the composites. The mobility of the P3HT TFT was approximately $10^{-4}cm^2/V{\cdot}s$. However, the mobility of the ZnO nanowire/P3HT composite TFT was increased by two orders compared to that of the P3HT TFT. In terms of the $I_{on}/I_{off}$ ratio, the composite device showed a two-fold increase compared to that of the P3HT TFT.

• Applied Chemistry for Engineering
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• v.10 no.6
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• pp.913-916
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• 1999

Fluorine modified diisocyanate(FMD) was synthesized from tris(6-isocyanatohexyl)isocyanurate(TIHI) and N-ethyl-N-2-hydroxyethyl-perfluorooctanesulfonamide(HFA). Fluorine modified polyurethane(FMPU) was also synthesized from FMD and poly(tetramethylene) glycol(PTMG). Modified polyurethanes were made by blending FMPU into the polyester type base polyurethane(BPU). Surface and thermal properties of the blended BPU film was measured by contact angle measurement and DSC. As the amounts of FMPU was increased from 0 wt % to 1 wt %, the surface energy was dramatically decreased from 47.82 dyne/cm to 17.64 dyne/cm. But we observed little change of the contact angle with further increase in the amount of the FMPU up to 10 wt %. The data meant that the surface of the blended polyurethanes was hydrophobic due to the surface arrangement of the fluorine containing moiety in FMPU. Phase separation was induced by the incompatibility of FMPU and BPU for the samples having over 5 wt % of FMPU. The thermal analysis data of these samples showed the thermal behavior of the FMPU itself.