• Proceedings of the KSME Conference
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• 2007.05a
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• pp.343-348
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• 2007

Molecular dynamics study of thermal NIL (Nano Imprint Lithography) process is performed to examine stamp-resist interactions. A layered structure consists of Ni stamp, poly-(methylmethacrylate) thin film resist and Si substrate was constructed for isothermal ensemble simulations. Imposing confined periodicity to the layered unit-cell, sequential movement of stamp followed by NVT simulation was implemented in accordance with the real NIL process. Both vdW and electrostatic potentials were considered in all non-bond interactions and resultant interaction energy between stamp and PMMA resist was monitored during stamping and releasing procedures. As a result, the stamp-resist interaction energy shows repulsive and adhesive characteristics in indentation and release respectively and irregular atomic concentration near the patterned layer were observed. Also, the spring back and rearrangement of PMMA molecules were analyzed in releasing process.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1071-1074
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• 2007

6Mask CMOS process in low temperature polycrystalline silicon thin film transistors (poly-Si TFTs) has been developed and verified by manufacturing a 6Mask CMOS AMLCD panel. The novel 6Mask CMOS process is realized by eliminating the storage mask, gate mask and via open mask of conventional structure.

• Korean Journal of Materials Research
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• v.8 no.1
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• pp.85-91
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• 1998

인이 높은 농도로 도핑되어진 LPCVD 다결정 실리콘 박막의 열팽창 계수를 마이크로 게이지법을 이용하여 측정하였다. 기존의 박막의 열팽창 계수 측정 법에서는 박막이 기판에 증착되어진 상태에서 측정이 이루어지므로, 기판의 탄성계수와 열팽창계수를 미리 알고 있어야 한다. 이에 비해 마이크로 게이지법에서는 박막의 열\ulcorner창 계수를 도출하기 위하여 기판의 탄성계수 값과 열팽창 계수 값을 필요로 하지 않는다는 장점이 있다. 마이크로 게이지법에서는 전류를 가할 경우 줄 발열에 의해 발생한 마이크로 게이지에의 변위를 측정하고, 그 때 계산된 마이크로 게이지의 평균 온도의 관계에서 열팽창 계수를 계산한다. 다결정 실리콘 박막의 열팽창 계수는 2.9 x $10^{-6}$$^{\circ}C$로 측정되었으며, 이 값들의 표준편차는 0.24x$10^{-6}$$^{\circ}C$였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.695-698
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• 2006

The photosensitive poly-siloxane material used as the passivation layers for the conventional back channel etched (BCE) thin film transistors (TFTs) has been investigated. Through the organic material, the TFT array fabrication process can be reduced and higher aperture ratio can be achieved for higher LCD panel performance. The interface between the organic passivation layer and the back channel of the amorphous active region has been improved by the back channel oxygen treatment and the devices exhibits lower leakage current than the conventional silicon nitride passivation layer of BCE TFTs. The leakage currents between Indium-tin-oxide (ITO) pixels and the TFT devices and its mechanism have also been investigated in this paper.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1287-1290
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• 2006

A high speed analog buffer using polycrystalline silicon (poly-Si) thin film transistors (TFT) is proposed for 2.2-inch quarter video graphic adapter (qVGA) TFT-LCD panel. Simulation results show that the settling time of the proposed circuit is $10{\mu}sec$ in 2.2-inch qVGA and the power consumption of proposed analog buffer is $25{\mu}W$.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.15 no.1
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• pp.25-32
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• 2009

It is now widely recognized that the disposal of packaging waste is an increasing environmental concern. Recent interest in polymer waste management of packaging materials has added incentive to the research. Poly(vinyl alcohol) is a readily biodegradable water-soluble polymer. However, this polymer cannot be processed by conventional extrusion technologies because the melting point of PVA is close to its decomposition temperature. Therefore, PVA films have been mostly prepared by solvent casting from water. Applications of PVA include sizing, binders, fibers, and films for agricultural chemicals and hospital laundry bags. A better understanding of PVA films, which also play important roles in the degradation of plastics, will expand the usage of PVA. Composite films based on PVA generally exhibit better mechanical and thermal properties than pure PVA. The aim of this review article is to review types, formation, and properties of PVA films and PVA based composite films used in packaging related researches.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1136-1139
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• 2009

Recently, various Ni doping systems and thermal annealing systems have been developed for fabrication of polycrystalline silicon film using SGS (super grain silicon) for medium and largesize AMOLED panels. In this study, we compare the potential of Ni doping systems including ALD (atomic layer deposition), AMD (atmospheric metal deposition), in-line sputter, and crystallization annealing systems including batch type furnace, inline furnace, and RTA (rapid thermal annealing) developed for the SGS method. Additional requirements for those systems to be used for mass production of large AMOLED TVs are suggested based on evaluation results for both poly-Si films and TFT backplanes.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.833-836
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• 2007

A low power and small area source driver using LTPS TFTs is proposed for mobile applications. This source driver adopts level shifter with holding latch function and new R-to-R type digital-to-analog converter (DAC). The power consumption and layout area of the proposed source driver are reduced by 23% and 25% for 16M colors and qVGA AM-OLED panel, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.16-19
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• 2007

In this paper, we present work that has been carried out using the SLS process to control grain boundary(GB) location in TFT channel region and it is possible to locate the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analyzed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.202-205
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• 1997

We investigated grain boundary effect for terrestrial applications of solar cell\ulcorner with low cost, large area, and high efficiency. Grain boundaries are known as potential barriers and recombination centers for the photo-generated charge carriers, which make it difficult to achieve a high efficiency cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatments, various grid patterns, selective wet etchings for grain boundaries, buried contact metallizations along grain boundaries, and use of metallic thin films. From the various grid patterns we learned that the series resistance of solar cell reduced open circuit voltage and consequently decreased the cell efficiency. This paper describes the effect of various grid patterns and the employment of metallic thin films for a top electrode.