• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.283-284
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• 2008

Electrical and optical characteristics of indium tin oxide (ITO) and indium zinc oxide (IZO) films without and with $(SiO_2)_3(ZnO)_7$ at.% (SZO) film deposited on poly(ethylene naphthalate) (PEN) and poly(ethylene terephthalate (PET) substrates as a gas barrier layer for flexible display were studied. The ITO and IZO films with SZO gas barrier layer showed the improved properties which were both the high transmittance of average 80% in the visible light range and the decreased sheet resistance as compared to those of ITO and IZO films without SZO layer. Particularly, the PEN substrate with only SZO gas barrier layer had a low water vapor transmission rate (WVTR) of $\sim10^{-3}g/m^2$/day. Thus, we suggest that the SZO film with protection ability against the water vapor permeation can be applied to gas barrier layer for flexible display.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.199-199
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• 2010

최근 평판 디스플레이 산업의 발전에 따라 능동행렬 액정 표시 소자 (AMOLED : Active Matrix Organic Liquid Crystral Display) 가 차세대 디스플레이 분야에서 각광을 받고있다. 기존의 TFT-LCD에 사용되는 a-Si:H는 균일도가 좋지만 전기적인 스트레스에 의해 쉽게 열화되고 낮은 이동도는 갖는 단점이 있으며, ELA (Eximer Laser Annealing) 결정화 poly-Si은 전기적인 특성은 좋지만 uniformity가 떨어지는 단점을 가지고 있어서 AMOLED 및 대면적 디스플레이에 적용하기 어렵다. 따라서 a-Si:H TFT보다 좋은 전기적인 특성을 보이며 ELA 결정화 poly-Si TFT보다 좋은 uniformity를 갖는 SPC (Solid Phase Crystallization) poly-Si TFT가 주목을 받고있다. 본 연구에서는 차세대 디스플레이 적용을 위해서 glass 기판위에 증착된 a-Si을 SPC 로 결정화 시킨 후 TFT를 제작하고 평가하였다. 또한 TFT 형성시에 저온공정을 실현하기 위해서 소스/드레인 영역에 실리사이드를 형성시켰다. 소자 제작시의 최고온도는 $500^{\circ}C$ 이하에서 공정을 진행하는 저온 공정을 실현하였다. Glass 기판위에 a-Si이 80 nm 증착된 기판을 퍼니스에서 24시간 동안 N2 분위기로 약 $600^{\circ}C$ 에서 결정화를 진행하였다. 노광공정을 통하여 Active 영역을 형성시키고 E-beam evaporator를 이용하여 약 70 nm 의 Pt를 증착시킨 후, 소스와 드레인 영역의 실리사이드 형성은 N2 분위기에서 $450^{\circ}C$, $500^{\circ}C$, $550^{\circ}C$에서 열처리를 통하여 형성하였다. 게이트 절연막은 스퍼터링을 이용하여 SiO2를 약 15 nm 의 두께로 증착하였다. 게이트 전극의 형성을 위하여 E-beam evaporator 을 이용하여 약 150 nm 두께의 알루미늄을 증착하고 노광공정을 통하여 게이트 영역을 형성 후 에 $450^{\circ}C$, H2/N2 분위기에서 약 30분 동안 forming gas annealing (FGA)을 실시하였다. 제작된 소자는 실리사이드 형성 온도에 따라서 각각 다른 특성을 보였으며 $450^{\circ}C$에서 실리사이드를 형성시킨 소자는 on currnet와 SS (Subthreshold Swing)이 가장 낮은것을 확인하였다. $500^{\circ}C$와 $550^{\circ}C$에서 실리사이드를 형성시킨 소자는 거의 동일한 on current와 SS값을 나타냈다. 이로써 glass 기판위의 SB-TFT 제작 시 실리사이드 형성의 최적온도는 $500^{\circ}C$로 생각되어 진다. 위의 결과를 토대로 본 연구에서는 SPC 결정화 방법을 이용하여 SB-TFT를 성공적으로 제작 및 평가하였고, 차세대 디스플레이에 적용할 경우 우수한 특성이 기대된다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.200-200
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• 2003

Polycrystalline Si(polysilicon) TFTs have opened a way for the next generation of display devices, due to their higher mobility of charge carriers relative to a-Si TFTs. The polysilicon W applications extend from the current Liquid Crystal Displays to the next generation Organic Light Emitting Diodes (OLED) displays. In particular, the OLED devices require a stricter control of properties of gate oxide layer, polysilicon layer, and their interface. The polysilicon layer is generally obtained by annealing thin film a-Si layer using techniques such as solid phase crystallization and excimer laser annealing. Typically laser-crystallized Si films have grain sizes of less than 1 micron, and their electrical/dielectric properties are strongly affected by the presence of grain boundaries. Impedance spectroscopy allows the frequency-dependent measurement of impedance and can be applied to inteface-controlled materials, resolving the respective contributions of grain boundaries, interfaces, and/or surface. Impedance spectroscopy was applied to laser-annealed Si thin films, using the electrodes which are designed specially for thin films. In order to understand the effect of grain size on physical properties, the amorphous Si was exposed to different laser energy densities, thereby varying the grain size of the resulting films. The microstructural characterization was carried out to accompany the electrical/dielectric properties obtained using the impedance spectroscopy, The correlation will be made between Si grain size and the corresponding electrical/dielectric properties. The ramifications will be discussed in conjunction with active-matrix thin film transistors for Active Matrix OLED.

• Korean Journal of Materials Research
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• v.20 no.11
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• pp.600-605
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• 2010

In order to meet the requirements of faster speed and higher packing density for devices in the field of semiconductor manufacturing, the development of Cu/Low k device material is explored for use in multi-layer interconnection. SiOC(-H) thin films containing alkylgroup are considered the most promising among all the other low k candidate materials for Cu interconnection, which materials are intended to replace conventional Al wiring. Their promising character is due to their thermal and mechanical properties, which are superior to those of organic materials such as porous $SiO_2$, SiOF, polyimides, and poly (arylene ether). SiOC(-H) thin films containing alkylgroup are generally prepared by PECVD method using trimethoxysilane as precursor. Nano voids in the film originating from the sterichindrance of alkylgroup lower the dielectric constant of the film. In this study, methyltriphenylsilane containing bulky substitute was prepared and characterized by using NMR, single-crystal X-ray, GC-MS, GPC, FT-IR and TGA analyses. Solid-state NMR is utilized to investigate the insoluble samples and the chemical shift of $^{29}Si$. X-ray single crystal results confirm that methyltriphenylsilane is composed of one Si molecule, three phenyl rings and one methyl molecule. When methyltriphenylsilane decomposes, it produces radicals such as phenyl, diphenyl, phenylsilane, diphenylsilane, triphenylsilane, etc. From the analytical data, methyltriphenylsilane was found to be very efficient as a CVD or PECVD precursor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1443-1445
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• 1996

Hydrogen passivation enhances the electrical characteristics of poly-Si TFT(Thin Film Transistor). However, the weak Si-H bonds, generated during hydrogenation, degrade the stability of the device. So, we carried out the passivation treatment with $NH_3$ or $N_2$. We compared the effect of $NH_3$ or $N_2$ passivation treatments with that of hydrogenation in terms of stability. Through the $NH_3$ passivation treatment, we obtained the most improved subthreshold swing of 1.2V/decade from the initial subthreshold swing of 1.56V/decade. When electrical stress was given, the $NH_3$ passivated devices showed best electrical stability.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Bulletin of the Korean Chemical Society
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• v.29 no.7
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• pp.1349-1352
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• 2008

We report a novel patterning method for a homo-polymeric poly(3-hexylthiophene) (P3HT) nanofilm particularly capable of strong adhesion to a $SiO_2$ surface. An oxidized silicon wafer substrate was micro-contact printed with n-octadecyltrichlorosilane (OTS) monolayer, and subsequently its negative pattern was selfassembled with three different amino-functionalized alkylsilanes, (3-aminopropyl)trimethoxysilane (APS), N- (2-aminoethyl)-3-aminopropyltrimethoxy silane (EDAS), and (3-trimethoxysilylpropyl) diethylenetriamine (DETAS). Then, P3HT nanofilms were selectively grown on the aminosilane pre-patterned areas via the vapor phase polymerization method. To evaluate the adhesion, patterning, and the film itself, the PEDOT nanofilms and SAMs were investigated with a $Scotch^{(R)}$ tape test, contact angle analyzer, ATR-FT-IR, and optical and atomic force microscopes. The evaluation showed that the newly developed all bottom-up process can offer a simple and inexpensive patterning method for P3HT nanofilms robustly adhered to an oxidized Si wafer surface by the mediation of $FeCl_3$ and amino-functionalized alkylsilane SAMs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.05a
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• pp.173-176
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• 2005

Teijin사의 HT100-B60의 폴리카보네이트(polycarbonate) $100{\mu}m$, I-Component사의 PES(polyethersulfone) $200{\mu}m$, Ferrania사의 PAR(polyacrylate) $100{\mu}m$와 $200{\mu}m$를 사용하였다 열팽창계수의 차이로 인해 공정상 기판의 가열과 냉각시 열응력이 발생하여 기판의 크랙발생의 원인이 된다. 이를 최소화하기 위해 모든 공정이 시작하기 전에 pre-annealing을 통해 plastic 기판의 시간별 공정을 실시하였다. plastic film의 annealing time은 0h, 12h, 24, 40h, 50h, 60h, 70h, 80h으로 사간을 달리하여 오븐 안의 진공상태를 조성하여 실험하였다. Thermal evaporator로 Al을 약 170nm 증착하였으며 (주)동진 세미캠의 DTFR-1011s DR LCD용 감광액을 Spin Coating Spread(500rpm/6sec), Spin(3000rpm/20sec)으로 coating하였다.

• Transactions on Electrical and Electronic Materials
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• v.13 no.1
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• pp.35-38
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• 2012

In this study, we have attempted to characterize the photovoltaic effect in real-time measurement of photoinduced current in a poly-Si-based solar cell using photoconductive atomic force microscopy (PC-AFM). However, the high contact resistance that originates from the metal-semiconductor Schottky contact disturbs the current flow and makes it difficult to measure the photoinduced current. To solve this problem, a thin metallic film has been coated on the surface of the device, which successfully decreases the contact resistance. In the PC-AFM analysis, we used a metal-coated conducting cantilever tip as the top electrode of the solar cell and light from a halogen lamp was irradiated on the PC-AFM scanning region. As the light intensity becomes stronger, the current value increases up to $200{\mu}A$ at 80 W, as more electrons and hole carriers are generated because of the photovoltaic effect. The ratio of the conducting area at different conditions was calculated, and it showed a behavior similar to that generated by a photoinduced current. On analyzing the PC-AFM measurement results, we have verified the correlation between the light intensity and photoinduced current of the poly-Si-based solar cell in nanometer scale.