• 제목/요약/키워드: polished wafer

검색결과 62건 처리시간 0.032초

Polished Wafer와 Epi-Layer Wafer의 표면 처리에 따른 표면 화학적/물리적 특성 (Comparison on the Physical & Chemical Characteristics in Surface of Polished Wafer and Epi-Layer Wafer)

  • 김진서;서형탁
    • 한국재료학회지
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    • 제24권12호
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    • pp.682-688
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    • 2014
  • Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

실리콘 웨이퍼 연마헤드의 강제구동 방식이 웨이퍼 연마 평탄도에 미치는 영향 연구 (Effects of Forced Self Driving Function in Silicon Wafer Polishing Head on the Planarization of Polished Wafer Surfaces)

  • 김경진;박중윤
    • 반도체디스플레이기술학회지
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    • 제13권1호
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    • pp.13-17
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    • 2014
  • Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

실험계획법을 적용한 웨이퍼 폴리싱의 최적 조건 선정에 관한 연구 (The Selection on the Optimal Condition of Si-wafer final Polishing by Combined Taguchi Method and Respond Surface Method)

  • 원종구;이정훈;이정택;이은상
    • 한국공작기계학회논문집
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    • 제17권1호
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    • pp.21-28
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    • 2008
  • The final polishing process is based on slurry, pad, conditioner, equipment. Therefore, the concept of wafer final polishing is also necessary for repeatability of results between polished wafers. In this study, the machining conditions have a pressure, table speed, machining time and slurry ratio. This research investigated the surface characteristics that apply variable machining conditions and response surface methodology was used to obtain more flexible and optimumal condition base on Taguchi method. On the base of estimated response surface curvature from the equation and results of Taguchi method, combined design of experiment was considered to lead to optimumal condition. Finally, polished wafer was obtained mirror like surface.

CMP 가공된 사파이어웨이퍼의 웨이퍼내 표면전위에 관한 연구 (A Study on the Zeta-potential of CMP processed Sapphire Wafers)

  • 황성원;신귀수;김근주
    • 한국정밀공학회지
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    • 제22권2호
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    • pp.46-52
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    • 2005
  • The sapphire wafer was polished by the implementation of the surface machining technology based on nano-tribology, The removal process has been performed by grinding, lapping and chemical-mechanical polishing. For the chemical mechanical polishing process, the chemical reaction between the slurry and sapphire wafer was investigated in terms of the change of Zeta-potential between two materials. The Zeta-potential was -4.98 mV without the slurry in deionized water and was -37.05 mV for the slurry solution. By including the slurry into the deionized water the Zeta-potential -29.73 mV, indicating that the surface atoms of sapphire become more repulsive to be easy to separate. The average roughness of the polished surface of sapphire wafer was ranged to 1∼4$\AA$.

Silicon/Pad Pressure Measurements During Chemical Mechanical Polishing

  • Danyluk, Steven;Ng, Gary;Yoon, In-Ho;Higgs, Fred;Zhou, Chun-Hong
    • 한국윤활학회:학술대회논문집
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    • 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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    • pp.433-434
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    • 2002
  • Chemical mechanical polishing refers to a process by which silicon and partially-processed integrated circuits (IC's) built on silicon substrates are polished to produce planar surfaces for the continued manufacturing of IC's. Chemical mechanical polishing is done by pressing the silicon wafer, face down, onto a rotating platen that is covered by a rough polyurethane pad. During rotation, the pad is flooded with a slurry that contains nanoscale particles. The pad deforms and the roughness of the surface entrains the slurry into the interface. The asperities contact the wafer and the surface is polished in a three-body abrasion process. The contact of the wafer with the 'soft' pad produces a unique elastohydrodynamic situation in which a suction force is imposed at the interface. This added force is non-uniform and can be on the order of the applied pressure on the wafer. We have measured the magnitude and spatial distribution of this suction force. This force will be described within the context of a model of the sliding of hard surfaces on soft substrates.

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단면 연마된 실리콘 웨이퍼의 열에 의한 휨 거동 (Thermal Warpage Behavior of Single-Side Polished Silicon Wafers)

  • 김준모;구창연;김택수
    • 마이크로전자및패키징학회지
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    • 제27권3호
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    • pp.89-93
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    • 2020
  • 반도체 패키지의 경박단소화로 인해 발생하는 복잡한 휨 거동은 내부 응력을 발생시켜 박리나 균열과 같은 다양한 기계적인 결함을 야기한다. 이에 따른 수율 감소를 막기 위해 휨 거동을 정확하게 예측하려는 노력은 다양한 측면에서 그 접근이 이루어지고 있다. 이 중 패키지를 구성하는 주 재료인 실리콘 웨이퍼는 일반적으로 균질한 물질로 취급되어 열에 의한 휨 거동은 전혀 없는 것으로 묘사된다. 그러나 실리콘을 얇게 가공하기 위해서 진행되는 그라인딩과 폴리싱에 의해 상온에서 휨이 발생한다는 사실이 보고되어 있고, 이는 표면에 형성되는 damage layer가 두께 방향으로 불균질함을 발생시키는 것으로부터 기인한다. 이에 본 논문에서는 반도체 패키징 공정 중 최고온 공정 과정인 solder reflow 온도에서 단면 연마된 웨이퍼가 나타내는 휨 거동을 측정하고, 이러한 휨 량이 나타나는 원인을 연마된 면과 그렇지 않은 면의 열팽창계수를 측정함으로써 밝혀내었다. 측정에는 미세 변형률과 형상이 모두 측정 가능한 3차원 디지털 이미지 상관법(Digital Image Correlation; DIC)을 이용하였다.

CMP와 Spin Etching에 의한 Blanket Wafer(TEOS) 가공 특성 비교에 관한 연구 (A Study on Machining Characteristic Comparison of Blanket Wafer(TEOS) by CMP and Spin Etching)

  • 김도윤;정해도;이은상
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2001년도 춘계학술대회 논문집
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    • pp.1068-1071
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    • 2001
  • Recently, the minimum line width shows a tendancy to decrease and the multi-level to increase in semiconductor. Therefore, a planarization technique is needed, which chemical polishing(CMP) is considered as one of the most important process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as microscratches, abrasive contaminations, and non-uniformity of polished wafer edges. Spin Etching can improve the defects of CMP. It uses abrasive-free chemical solution instead of slurry. Wafer rotates and chemical solution is simultaneously dispensed on a whole surface of the wafer. Thereby chemical reaction is occurred on the surface of wafer, material is removed. On this study, TEOS film is removed by CMP and Spin Etching, the results are estimated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU).

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습식 에칭에 의한 웨이퍼의 층간 절연막 가공 특성에 관한 연구 (A Study on a Wet etching of ILD (Interlayer Dielectric) Film Wafer)

  • 김도윤;김형재;정해도;이은상
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.935-938
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    • 1997
  • Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

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