• Journal of the Korean Crystal Growth and Crystal Technology
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• v.15 no.1
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• pp.34-38
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• 2005

Effects of pH level and slurry particle size on material removal rate and planarization of langasite single crystal wafer have been examined. Higher material removal rate was obtained with lower pH level slurries while the planarization was found to be determined by average particle size of colloidal silica slurries. Slurries containing 0.045 ㎛ amorphous silica particles showed the best polishing effect without any scratches on the surface. Effective particle number has a strong effect on the surface planarization and the removal rate, so that the lower effective particle numbers produced low removal rate but the better planarization results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1084-1090
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• 1998

As device sizes are scaled down to submicron dimensions, planarization technology becomes increasingly important for both device fabrication and formation of multilevel interconnects. Chemical mechanical polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. The polishing process has many variables, and most of which are not well understood. The factors determine the planarization performance are slurry and pad type, insert material, conditioning technique, and choice of polishing tool. Circuit density, pattern size, and wiring layout also affect the performance of a CMP planarization process. This paper presents the results of studies on CMP process window characterization for 0.35 micron process with 5 metal layers.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.21-27
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• 1995

AI planarization 공정을 위한 barrier로서 CVD 및 PVD 방법에 의해 증착된 TiN 박막의 특성에 대하여 연구하였다. CVD TiN은 TDMAT source를 사용한 MOCVD방법으로 증착하였으며, PVD TiN은 1:1 aspect ratio(A/R)를 갖는 collimator를 사용한 reactive wputtering법으로 증착하였다. AES, SEM을 이용하여 CVD TiN과 PVD TiN의 조성을 분석하고 barrier 특성을 평가하였다. CVD TiN, PVD TiN 모두 400$\AA$의 두께와 RTA 처리에 의해서 AI planarization에 대한 양호한 barrier 특성을 확보할 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.76-82
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• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.167-171
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• 1996

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily achieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etchback process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurement of planarity. Moreover, it will contribute to analyze planarization characteristics and establish CMP model.

• ETRI Journal
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• v.36 no.5
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• pp.847-855
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• 2014

We developed a highly refractive index planarization layer showing a very smooth surface for organic light-emitting diode (OLED) light extraction, and we successfully prepared a highly efficient white OLED device with an embossed nano-structure and highly refractive index planarization layers. White OLEDs act as an internal out-coupling layer. We used a spin-coating method and two types of $TiO_2$ solutions for a planarization of the embossed nano-structure on a glass substrate. The first $TiO_2$ solution was $TiO_2$ sol, which consists of $TiO_2$ colloidal particles in an acidic aqueous solution and several organic additives. The second solution was an organic and inorganic hybrid solution of $TiO_2$. The surface roughness ($R_a$) and refractive index of the $TiO_2$ planarization films on a flat glass were 0.4 nm and 2.0 at 550 nm, respectively. The J-V characteristics of the OLED including the embossed nano-structure and the $TiO_2$ planarization film were almost the same as those of an OLED with a flat glass, and the luminous efficacy of the aforementioned OLED was enhanced by 34% compared to that of an OLED with a flat glass.

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.51-51
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• 2000

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.546-550
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• 2004

Two fabrication approaches are proposed to planarize the sacrificial layer over hollow structures. One is the photoresist filling method that makes use of photolithography, thermal curing and plasma ashing. The other is the lamination method that is applying pressure and temperature to the organic film over the hollow structures. The fabrication results are compared with those of CMP process. Trenches and cavities with various dimensions have been made for the porposed process. Upon measuring the planarization levels, they are dependent on planarization methods and the geometrical size of hollow structures. The photoresist filling method is so strongly dependent on the width and depth of trenches that we have problems to use it for large dimensional trenches. To the contrary, the flatness of sacrificial layer over the trenches was found to be almost independent of trench dimensions for the lamination method. A CMP process shows the most excellent results, but the fabrication is complicated and the access to it is not so easy. It is important to choose the proper planarization method by considering the required flatness levels, materials to be planarized, and connection between the planarization step and the previous or the following process of it.

• Tribology and Lubricants
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• v.37 no.6
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• pp.213-223
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• 2021

Electrochemical mechanical planarization (ECMP) was developed to overcome the shortcomings of conventional chemical mechanical planarization (CMP). Because ECMP technology utilizes electrochemical reactions, it can have a higher efficiency than CMP even under low pressure conditions. Therefore, there is an advantage in that it is possible to reduce dicing and erosions, which are physical defects in semiconductor CMP. This paper summarizes the papers on ECMP published from 2003 to 2021 and analyzes research trends in ECMP technology. First, the material removal mechanisms and the configuration of the ECMP machine are dealt with, and then ECMP research trends are reviewed. For ECMP research trends, electrolyte, processing variables and pads, tribology, modeling, and application studies are investigated. In the past, research on ECMP was focused on basic research for the development of electrolytes, but it has recently developed into research on tribology and process variables and on new processing systems and applications. However, there is still a need to increase the processing efficiency, and to this end, the development of a hybrid ECMP processing method using another energy source is required. In addition, ECMP systems that can respond to the developing metal 3D printing technology must be researched, and ECMP equipment technology using CNC and robot technology must be developed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.456-460
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• 1997

As device sizes are scaled to submicron dimensions, planarization technology becomes increasing1y important, both during device fabrication and during formation of multilevel interconnects and wiring. Chemical Mechanical Polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. This paper is presented the results of CMP process window characterization studies for 0.35 micron process with 6 metal layers.