• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2433-2452
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• 2017

Recently, the pipeline-forwarding has been proposed as a new technique to resolve the end-to-end latency problem of the duty-cycle MAC protocols in Wireless Sensor Networks (WSNs). Some protocols based on this technique such as PMAC and PRI-MAC have shown an improvement not only in terms of reducing end-to-end latency but also in terms of reducing power consumption. In these protocols, however, the sensor nodes still waste a significant amount of energy for unnecessary idle listening during contention period of upstream nodes to check the channel activity. This paper proposes a new pipeline-forwarding duty-cycle MAC protocol, named RP-MAC (Reduced Pipelined duty-cycle MAC), which tries to reduce the waste of energy. By taking advantage of ACK mechanism and shortening the handshaking procedure, RP-MAC minimizes the time for checking the channel and therefore reduces the energy consumption due to unnecessary idle listening. When comparing RP-MAC with the existing solution PRI-MAC and RMAC, our QualNet-based simulation results show a significant improvement in term of energy consumption.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.200-203
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• 2000

In this paper, we describes the design of a CPU compatible with ARM9 processor. The CPU is fully synthesizable and described in Verilog-XL. Starting from the synthesizable ARM7 compatible CPU we developed earlier, we modified its pipeline to five stages. For this we first partition the behaviors of each instruction into five stage pipeline operations. Then we designed the controller and the datapath considering the forwarding or interlock schemes. Finally the compatibility of the designed CPU is verified by comparing the results of every instruction executed in test programs with those of the reference simulator developed for the ARM7 compatible CPU.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.53-67
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• 1994

This paper describes the design of a high-level synthesis system. SODAS-VP. which automatically generates hardwares executing operation sequences in pipelined fashion.Target architecture and clocking schemes to drive pipelined datapath are determined, and the handling of pipeline hazards which degrade the performance of pipeline is considered. Partitioning of an operation into load, operation, and store stages, each of which is executed in partitiones control step, is performend. Pipelinecl hardware is generated by handling pipeline hazards with internal forwarding or delay insertion techniques in partitioning process and resolving resource conflicts among the partitioned control steps with similarity measure as a priority function in module allocation process. Experimental results show that SODAS-VP generates hardwares that execute faster than those generated by HAL and ALPS systems. SODAS-VP brings improvement in execution speed by 17.1% and 7.4% comparing with HAL and ALPS systems for a MCNC benchmark program, 5th order elliptical wave filter,respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.244-253
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• 2000

Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.