• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.144-147
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• 2004

Two different sensors (here, KOMPSAT and RADARSAT) are considered for ship detection, and are used to delineate the detection performance for their data. The experiments are set for coastal regions of Mokpo Port and Ulsan Port and field experiments on board pilot boat are conducted to collect in situ ship validation information such as ship type and length. This paper introduce mainly the experiment result of ship detection by both RADARSAT SAR imagery and landbased RADAR data, operated by the local Authority of South Korea, so called vessel traffic system (VTS) radar. Fine imagery of Ulsan Port was acquired on June 19, 2004 and in-situ data such as wind speed and direction, taking pictures of ships and natural features were obtained aboard a pilot ship. North winds, with a maximum speed of 3.1 m/s were recorded. Ship's position, size and shape and natural features of breakwaters, oil pipeline and alongside ship were compared using SAR and VTS. It is shown that KOMPSAT/EOC has a good performance in the detection of a moving ship at a speed of 7 kts or more an hour that ship and its wake can be imaged. The detection capability of RADARSAT doesn't matter how fast ship is running and depends on a ship itself, e.g. its material, length and type. Our results indicate that SAR can be applicable to automated ship detection for a VTS and SAR combination service.

• Proceedings of KOSOMES biannual meeting
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• 2004.11a
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• pp.43-47
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• 2004

Two different sensors (here, KOMPSAT and RADARSAT) are considered for ship detection, and are used to delineate the detection performance for their data The experiments are set for coastal regions of Mokpo Port and Ulsan Port and field experiments on board pilot boat are conducted to collect in situ ship validation information such as ship type and length This paper introduce mainly the experiment result of ship detection by both RADARSAT SAR imagery and land-based RADAR data, operated by the local Authority of South Korean, so called vessel traffic system (VTS) radar. Fine imagery of Ulsan Port was acquired on June 19, 2004 and in-situ data such as wind speed and direction, taking pictures of ships and natural features were obtained aboard a pilot ship. North winds, with a maximum speed of 3.1 m/s were recorded Ship's position, size and shape and natural features of breakwaters, oil pipeline and alongside ship were compared using SAR and VTS. It is shown that KOMPSAT/EOC has a good performance in the detection of a moving ship at a speed of kts or more an hour that ship and its wake can be imaged. The detection capability of RADARSAT doesn't matter how fast ship is running and depends on a ship itself, e.g. its material, length and type. Our results indicate that SAR can be applicable to automated ship detection for a VTS and SAR combination service.

• Korean Journal of Computational Design and Engineering
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• v.16 no.6
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• pp.437-448
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• 2011

A robotic spatial augmented reality (RSAR) system combines a robotics technology with a spatial augmented reality system (SAR) where cameras are used to recognize real objects and projectors augment information and user interface directly on the surface of the recognized objects, rather than relying on handheld display devices. Moreover, a robotic module is actively used to discover and utilize the context of users and environments. The control of a RSAR system involves several issues from different technical fields such as classical inverse kinematics of motors where projector-camera pairs are mounted, inverse projection problems to find appropriate internal/external parameters of projectors and cameras, and image warping in graphics pipeline to compensate the kinematic constraints. In this paper, we investigate various control issues related to a RSAR system and propose basic approaches to handle them, specially focused on the prototype RSAR system developed in ETRI.