• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.1-6
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• 2021

The paper proposes the design of AES-based encryption chip for IoT security. ROM based S-Box implementation occurs a number of memory space and some delay problems for its access. In this approach, S-Box is designed by pipeline structure on composite field GF((22)2) to get faster calculation results. In addition, in order to achieve both higher throughput and less delay, shared S-Box are used in each round transformation and the key scheduling process. The proposed AES crypto-processor is described in Veilog-HDL, and Xilinx ISE 14.7 tool is used for logic synthesis by using Xilinx XC6VLX75T FPGA. In order to perform the verification of the crypto-processor, the timing simulator(ModelSim 10.3) is also used.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.1
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• pp.71-83
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• 2020

In this paper, we propose a system that can detect the shape of a hand at high speed using an FPGA. The hand-shape detection system is designed using Verilog HDL, a hardware language that can process in parallel instead of sequentially running C++ because real-time processing is important. There are several methods for hand gesture recognition, but the image processing method is used. Since the human eye is sensitive to brightness, the YCbCr color model was selected among various color expression methods to obtain a result that is less affected by lighting. For the CbCr elements, only the components corresponding to the skin color are filtered out from the input image by utilizing the restriction conditions. In order to increase the speed of object recognition, a median filter that removes noise present in the input image is used, and this filter is designed to allow comparison of values and extraction of intermediate values at the same time to reduce the amount of computation. For parallel processing, it is designed to locate the centerline of the hand during scanning and sorting the stored data. The line with the highest count is selected as the center line of the hand, and the size of the hand is determined based on the count, and the hand and arm parts are separated. The designed hardware circuit satisfied the target operating frequency and the number of gates.

• Journal of the Korean Recycled Construction Resources Institute
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• v.5 no.3
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• pp.84-93
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• 2010

Compaction of backfill material of Underground power lines is difficult, especially under pipeline. so it could cause structural problem because of low compaction efficiency. So various methods have been taken to solve the problem and one of them is CLSM(Controled low-strength material accelerated flow ability). But In other countries, these are already in progress for a long time to research and development and recently on practical steps. But, in our country, study for only general structures, not for underground power line structure that is being constructed at night rapidly. In this study, we performed property tests and indoor & outdoor test (3 cases). The tests showed flow ability reached at the limit construction(160 mm) flowability by 9 to 15 minute after starting to mix, and construction buoyant is lowering after placing CLSM by 70 % of theoretical buoyant that is calculated by unit weight of material. In this paper, we performed indoor tests and outdoor tests to estimate mechanical properties and to suggest construction method(using batch plant, setting spacer at 1.8 m and placing at 2m) for CLSM that using surplus soil. And the test showed good results for construction quality, workability and structure safety.

• Journal of the Korean Geotechnical Society
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• v.37 no.10
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• pp.77-87
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• 2021

Several studies have been conducted to analyze, predict, and prevent the risk of ground subsidence occurring in urban areas. Nevertheless, there is insufficient research effort on risk analysis that utilizes the correlation between the density of underground structures (i.e., the spatial quantity of buried objects installed in the ground around the interested area) and the occurrence of ground subsidence. In this paper, a study was conducted to analyze the line density of underground structures using GIS-based spatial information data, and to link this with the recorded ground subsidences. An optimization algorithm was developed to maximize the correlation between the line density of 29 recorded ground subsidences and 6 types of underground structures that occurred between 2010 and 2015 for the analysis area. The concept of normalized line density was also proposed for the analysis. The normalized line density of the analysis area was divided into five grades (Grade 1: lowest, Grade 5: highest). When the optimization algorithm was applied, the case where the normalized line density was Grade 4 or higher at the location of the recorded ground subsidences was about > 80%. It is thought that the density analysis result of underground facilities can be applied to the ground subsidence risk analysis by using the proposed optimization algorithm.

• Journal of Korean Tunnelling and Underground Space Association
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• v.19 no.3
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• pp.421-435
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• 2017

Recently, due to the saturation of ground structures and the overpopulation of pipeline facilities requires to development of underground structures as an alternative to ground structures. Thus, mechanized tunnel construction of the shield TBM method has been increasing in order to prevent vibration and noise problems in construction of the NATM tunnel for the urban infrastructure construction. Tunnel construction plan for the tunnel line should be formed in a sharp curve to avoid building foundation and underground structures and it is inevitable to develop a shield TBM technology that suits the sharp curve tunnel construction. Therefore, this study is about the structural stability technology of the articulation jack, shield jack and skin plate for the shield TBM thrust in case of the mechanized tunnel construction that is a straight and sharp curve line. The construction case study and shield TBM operation principle are examined and analyzed by the theoretical approach. The torque of the cutter head, the thrust of the articulation jack and the shield jack, the amount of over cutting for curve is important respectively in shield TBM construction of straight and sharp curve line. In addition, it is very important to secure the stability of the skin plate structure to ensure the safety of the inside worker. This study examines the general structure and construction of the equipment, experimental simulation was carried out through numerical analysis to examine the main factors and structural stability of the skin plate structure. The structural stability of the skin plate was evaluated and optimizes the shape by comparing the loads of the articulation jack by selecting the virtual soil to be applied in a straight and sharp curve line construction. Since the present structure and operation method of the shield TBM type in domestic constructions are very similar, this study will help to develop the localized shield TBM technology for the new equipment and the vulnerability and stability review.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of KIISE:Databases
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• v.29 no.3
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• pp.180-192
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• 2002

We investigate the effect of the data skew of join attributes on the performance of a pipelined multi-way hash join method, and propose two new harsh join methods in the shared-nothing multiprocessor environment. The first proposed method allocates buckets statically by round-robin fashion, and the second one allocates buckets dynamically via a frequency distribution. Using harsh-based joins, multiple joins can be pipelined to that the early results from a join, before the whole join is completed, are sent to the next join processing without staying in disks. Shared nothing multiprocessor architecture is known to be more scalable to support very large databases. However, this hardware structure is very sensitive to the data skew. Unless the pipelining execution of multiple hash joins includes some dynamic load balancing mechanism, the skew effect can severely deteriorate the system performance. In this parer, we derive an execution model of the pipeline segment and a cost model, and develop a simulator for the study. As shown by our simulation with a wide range of parameters, join selectivities and sizes of relations deteriorate the system performance as the degree of data skew is larger. But the proposed method using a large number of buckets and a tuning technique can offer substantial robustness against a wide range of skew conditions.