• Proceedings of the KSR Conference
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• 2000.05a
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• pp.180-187
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• 2000

This paper presents the system of analyzing data in memory of TCMS. This system can show physical data in memory to text and graphic : format. To transfer data from TCMS to this system, a large number of system have used to memory IC card. the method of using memory IC card as a intermediation has many points at issue, that is a speed of transmitting data, life time of IC card and identity of train system each other. So this paper proposes that the method of wireless LAM be adopted by this system to improve the week point of previous method and other method to better the method of wireless LAN.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.94-100
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• 2008

It is necessary to develop the flash memory system software FTL(Flash Translation Layer) which is used in mobile storage like Compact Flash memory. In this paper, we design the FTL using clustered hash table and two phase software caching method to translate logical address into physical address fastly. The experimental results show that the address translation performance of CFTL is 13.3% higher than that of NFTL and 8% higher than that of AFTL, and the memory usage of CFTL is 75% smaller than that of AFTL.

• PNF and Movement
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• v.9 no.1
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• pp.55-63
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• 2011

Purpose : This study was to investigate the application of Rhythmic Initiation(RI) in the respect of information processing in motor learning. Methods : A computer-aided literature search was performed in PubMed and adapted to the other databases and the others were in published books. The following keywords were used: Rhythmic Initiation, attention, memory, motor accuracy, feedback, motor learning, motor control, PNF, cognition. Results : The characterization of RI is rhythmic motion of limb or body through the desired range, starting with passive motion and progressing to active resisted movement. This study suggested that the relationship between of RI and motor learning through the respect of information processing, memory, attention and motor accuracy. Conclusion : Only Rhythmic Initiation, specifically focused on the effects of information processing approach, suggesting that RI can be positively influeced on sensory-perception, attention, memory, motor accuracy. however, it is unclear whether positive effects in the laboratory and field can be generalized to improve. In addition, sustainability of motor learning with RI remains uncertain.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• Journal of the Korean Society of Physical Medicine
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• v.7 no.1
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• pp.11-20
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• 2012

Purpose : This study is intended to examine the repetitive transcranial magnetic stimulation on cognitive function in the focal ischemic stroke rat model. Methods : This study selected 30 Sprague-Dawley rats of 8 weeks. The groups were divided into two groups and assigned 15 rats to each group. Control group: Non-treatment after injured by focal ischemic stroke; Experimental group: application of repetitive transcranial magnetic stimulation(0.1 Tesla, 25 Hz, 20 min/time, 2 times/day, 5 days/2 week) after injured by focal ischemic stroke. To assess the effect of rTMS, the passive avoidance test, spatial learning and memory ability test were analyzed at the pre, 1 day, $7^{th}$ day, $14^{th}$ day and immunohistochemistric response of BDNF were analyzed in the hippocampal dentate gyrus at $7^{th}$ day, $14^{th}$ day. Results : In passive avoidance test, the outcome of experimental group was different significantly than the control group at the $7^{th}$ day, $14^{th}$ day. In spatial learning and memory ability test, the outcome of experimental group was different significantly than the control group at the $7^{th}$ day, $14^{th}$ day. In immunohistochemistric response of BDNF in the hippocampal dentate gyrus, experimental groups was more increased than control group. Conclusion : These result suggest that improved cognitive function by repetitive transcranial magnetic stimulation after focal ischemic stroke is associated with dynamically altered expression of BDNF in hippocampal dentate gyrus and that is related with synaptic plasticity.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.293-303
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• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.71-79
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• 2012

As advances in computer technology, dissemination of smartphones and tablet PCs has increased and digital media has become easily accessible. The performance of computer hardware is improved and the form of hardware is changed, but basically the change in mechanism was not occurred. Typically, the data used in the program is resident in memory during the operation because of the operating system efficiency. So, these data in memory is accessible through the memory dumps or real-time memory analysis. The user's personal information or confidential data may be leaked by exploiting data; thus, the countermeasures should be provided. In this paper, we proposed the method that minimizes user's data leakage through finding the physical memory address of the process using virtual memory address, and initializing memory data of the process.