• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.105-109
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• 2018

In this paper, the performance enhancement of a time-modulated array is described. The proposed time-modulated array is based on the topology of a conventional array but uses apodized discrete time switching, instead of phase shifters, to achieve beamforming functions with side-band suppression. Numerical simulations are carried out to examine the performance of this beamforming system based on apodized time sequence of 16 elements linear array. Numerical results reveal that the proposed method provides a more flexible and accurate way of producing desired beampatterns with low or ultralow side-lobe level (SLL) compared with the conventional methods.

• Korean Journal of Optics and Photonics
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• v.15 no.6
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• pp.591-596
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• 2004

In this paper, a photonic RF true-time delay based on a partially side-polished fiber Bragg grating with heating electrode has been proposed and fabricated. It features continuous voltage-controlled operation, requiring no mechanical perturbation and no moving parts. For an RF signal carried over an optical signal, the time delay has been obtained by controlling the voltage applied to the electrode and thus adjusting its reflection positions from the fiber grating via the thermooptic effect. The achieved time delay is about 100 ps with the electrical power consumption of 280 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.417-426
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• 2010

This paper describes the 6-way power divider to be used as a feeding structure of the waveguide array antenna generating the plane wave at the near distance. The SMA connector has been connected at the center of the power divider in order to feed the radiating element. The six output ports made of waveguide are positioned on the peripheral of the divider. This paper proposes the method utilizing the inductive post in order to decrease the return loss. The height of the feeding pin, the diameter of the inductive post, and the distance between the feeding pin and inductive post have been investigated, and as a result, the power divider has been optimized. The simulated and measured results show the low return loss of about -40 dB. The calculated and measured transmission coefficients are -7.78 dB and -8.06 dB, respectively. The output power of the six waveguide port show equal-amplitude and equal-phase distribution. Since the power divider proposed in this paper can be expanded to the divider having several output ports, it could be easily applied to the various array antennas.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.