• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• 한국항행학회논문지
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• 제9권2호
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• pp.140-146
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• 2005

본 논문에서는 HDR-WPAN 시스템에 적합한 주파수 옵셋 보상과 누적 위상오차를 개선할 수 있는 트래킹 알고리즘을 제안하고 이에 대해 분석하였다. 주파수 옵셋 보상 알고리즘은 CAZAC sequence의 자기상관 특성을 이용하여 각 심벌 내 샘플 간 위상오차를 통해 coarse 주파수 옵셋과 fine 주파수 옵셋을 추정하게 된다. 그러나 HDR-WPAN 시스템은 payload에 pilot 심벌이 없기 때문에 payload 길이가 길어질수록 샘플 간 미소 위상오차가 누적되어 수신단의 성상도가 회전하게 된다. 따라서 트래킹 알고리즘을 통해 틀어진 누적 위상오차를 보상해야 한다. 트래킹은 성상도내 들어온 신호가 일정 영역을 벗어나게 되면, 벗어난 만큼의 크기 ${\theta}$을 곱해 누적된 미소 위상오차를 보상하게 된다.

• 한국정보통신학회논문지
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• 제9권3호
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• pp.638-646
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• 2005

최근 무선통신시스템에서 직접변환 트랜시버 또는 IF 샘플링 SDR 기반 수신기가 일반적인 트랜시버 구조에 상응하여 설계되어지고 있다. 일반적인 AFC/APC 보상 회로가 기저 대역에서 RF 입력 신호와 국부발진 신호의 주파수 및 위상 오차를 보정할지라도 직접변환 수신 구조에서는 주요한 열화요소로 작용한다. 일반적인 보상 회로의 제한적인 동작 영역과 기저 대역에서의 1/Q 채널의 불평형을 용이하게 보상할 수 있도록 RF 입력 신호단에서 주파수 및 위상 오차를 보정하는 방법을 본 논문에서 제안한다. RF 입력단에서 고정된 주파수 및 위상 오차 이외에 변화하는 주파수 및 위상 오차를 제안된 early-late 보상기에 의해 효과적으로 보상할 수 있다. RF 입력단에서의 주파수 및 위상 오차의 보정으로 직접변환 수신기의 기저 대역에서의 기존 주파수 및 위상 오차 보정 회로는 간단히 설계할 수 있으며 미세한 오차 보정 구조로 용이하게 이용할 수 있다.

• 전기학회논문지
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• 제64권7호
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• 한국통신학회논문지
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• 제28권4C호
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• pp.384-391
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• 2003

Blind channel identification and equalization attempt to identify the communication channel and to remove the inter-symbol interference caused by a communication channel without using any known trainning sequences. In this paper, we propose a blind adaptive channel identification and equalization algorithm with phase offset compensation for single-input multiple-output (SIMO) channel. It is based on the one-step forward multichannel linear prediction error method and can be implemented by an RLS algorithm. Phase offset problem, we use a blind adaptive algorithm called the constant modulus derotator (CMD) algorithm based on condtant modulus algorithm (CMA). Moreover, unlike many known subspace (SS) methods or cross relation (CR) methods, our proposed algorithms do not require channel order estimation. Therefore, our algorithms are robust to channel order mismatch.

• Journal of Power Electronics
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• 제15권6호
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• pp.1593-1600
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• 2015

This paper proposes a novel compensation algorithm of current offset error for single-phase linear compressor in home appliances. In a half-bridge inverter, current offset error may cause unbalanced DC-link voltage when the DC-link is comprised of two serially connected capacitors. To compensate the current measurement error, the synchronous reference frame transformation is used for detecting the measurement error. When an offset error occurs in the output current of the half-bridge inverter, the d-axis current has a ripple with frequency equal to the fundamental frequency. With the use of a proportional-resonant controller, the ripple component can be removed, and offset error can be compensated. The proposed compensation method can easily be implemented without much computation and additional hardware circuit. The validity of the proposed algorithm is verified through experimental results.

• 전기학회논문지
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• 제65권7호
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• pp.1204-1210
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• 2016

The phase currents must be accurately measured to achieve the instantaneous torque control of AC motors. In general, those are measured using the current sensors. However, the measured current signals can include the offset errors and scaling errors by several components such as current sensors, analog amplifiers, noise filter circuits, and analog-to-digital converters. Therefore, the torque-controlled performance can be deteriorated by the current measurement errors. In this paper we have analyzed the influence caused by vector control of 2-phase induction motor when two errors are included in measured phase currents. Based on analyzed results, the compensation method is proposed without additional hardware. The proposed compensation method was applied vector-controlled inverter for 2-phase induction motor of 360[W] class and verified through computer simulations and experiments.

• 조명전기설비학회논문지
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• 제27권7호
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• pp.29-36
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• 2013

In this paper, a new DC offset elimination filter is proposed for an accurate phasor extraction of fundamental frequency component. The proposed method can eliminate a DC offset component which is decayed exponentially. The proposed method uses only one cycle of data for phasor extraction computation, which does not need to preset the time constant of the DC offset component. Also, the other advantages of the proposed method is that gain compensation or phase compensation is not required after filtering. Simulations using ATP were performed to evaluate the performance of the proposed filter method, and the results were compared to the ones obtained by conventional methods.

• 한국태양에너지학회 논문집
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• 제37권6호
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• Journal of Positioning, Navigation, and Timing
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• 제4권1호
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• pp.25-31
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• 2015

In this paper, we described the timing-offset comparison results between various daily jump compensation methods for GPS carrier phase (CP) measurement data. For the performance comparison, we used about 70 days GPS measurement data obtained from two GPS geodetic receivers which share the reference 1 PPS and RF signals and closely located in each other within a few meters. From the experiment results, the followings were observed. First, daily jumps existed in CP measurements depend on not only the environment but also the receiver which will make a full compensation be very hard or impossible. Second, clock bias can be occurred in the case of using a simple compensation with accumulation of daily jumps but it could be used in a short-period frequency comparison campaign (less than about 7 days) despite of its drawback.