• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1695-1699
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• 2012

This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.8
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• pp.536-543
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• 2000

The photovoltaic power generation system has a great future as clean energy instead of fossil fuel which has many environmental problems such as exhausted gas or air pollution. In a utility interactive photovoltaic generation system, a three-phase inverter is used for the connection between the photovoltaic array and the utility. This paper present a three phase inverter for photovoltaic power system with current controller, voltage controller, PLL Control system and the Phase detector of Interactive Voltage by using dq transformation. The proposed inverter system provides a sinusoidal ac current for domestic loads and the utility line with unity power factor.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.131-136
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• 2008

System을 통해 출력되는 신호를 측정할 때 정확한 측정을 방해하는 요소로 잡음이 있다. 이런 신호 측정의 방해 요소인 잡음을 제거 하는 방법 중의 하나로 Lock-in Amp(LIA)가 사용되고 있다. 본 논문에서는 잡음 신호의 제거를 위해 사용 하는 LIA를 제작 하고 특성을 파악 하였으며 RF통신을 이용하여 무선 형태로 제작 하였다. 현재 상용화된 LIA는 프로브를 통한 유선으로 측정신호의 입력을 받게 되지만 본 논문에서 제작된 LIA는 무선신호 형태로 입력 하게 된다. RF통신의 케리어 주파수는 447.9[MHz]로 Digital GMSK 변복조방식을 이용하였다. LIA의 제작은 Dual Phase Sensitive Detecter을 사용하였으며, 주요 구성 요소인 Phase Locked Loop, Phase Shifter, Phase Sensitive Detector, Low Pass Filter등의 구조와 특성을 조사하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Biotechnology and Bioprocess Engineering:BBE
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• v.9 no.1
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• pp.47-51
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• 2004

Ceramide III was prepared by the cultivation of Saccharomyces cerevisiae. Ceramide III was partitioned from the cell extracts by solvent extraction and analyzed by Normal Phase High Performance Liquid Chromatography (NP-HPLC) using Evaporative Light Scattering Detector (ELSD). We experimentally determined the mobile phase composition to separate ceramide III with NP-HPLC. Three binary mobile phases of n-hexane/ethanol, n-hexane/lsoprophyl Alcohol(IPA) and n-hexane/n-butanol and one ternary mobile phase of n-hexane/IPA/methanol were demonstrated. For the binary mobile phase of n-hexane/ethanol, the first mobile phase composition, 95/5(v/v), was step-increased to 72/23(v/v) at 3 min. In the binary mobile phase, the retention time of ceramide III was 7.87min, while it was 4.11 min respectively in the ternary system, where the mobile phase composition of n-hexane/IPA/methanol, 85/7/8(v/v/v), was step-increased to 75/10/15(v/v/v) at 3 min. However, in the ternary mobile phase, the more peak area of ceramide III was observed.

• International Journal of Ocean System Engineering
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• v.1 no.4
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• pp.205-210
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• 2011

High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Journal of the Optical Society of Korea
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• v.13 no.2
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• pp.245-250
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• 2009

We propose a digital holographic interference analysis method based on a 2-frame phase-shifting technique for measuring an optical mirror surface. The technique using 2-frame phase-shifting digital interferometry is more efficient than multi-frame phase-shifting techniques because the 2-frame method has the advantage of a reduced number of interferograms, and then takes less time to acquire the wanted topography information from interferograms. In this measurement system, 2-frame phase-shifting digital interferograms are acquired by moving the reference flat mirror surface, which is attached to a piezoelectric transducer, with phase step of 0 or $\pi$/2 in the reference beam path. The measurements are recorded on a CCD detector. The optical interferometry is designed on the basis of polarization characteristics of a polarizing beam splitter. Therefore the noise from outside turbulence can be decreased. The proposed 2-frame algorithm uses the relative phase difference of the neighbor pixels. The experiment has been carried out on an optical mirror which flatness is less than $\lambda$/4. The measurement of the optical mirror surface topography using 2-frame phase-shifting interferometry shows that the peak-to-peak value is calculated to be about $0.1779{\mu}m$, the root-mean-square value is about $0.034{\mu}m$. Thus, the proposed method is expected to be used in nondestructive testing of optical components.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.634-640
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• 2000

This paper proposes a new extended decision directed-decision estimated phase recovery algorithm based on maximum likelihood parameter estimation for OQPSK. In this scheme, comparing conventional one, the data dependent noise of phase recovery loop is reduced by inserting filter with 2 taps to in-phase and quadrature-phase channel respectively before phase detector. The proposed scheme is compared to conventionalscheme and OQPSK in aspect to BER(Bit Error Rate) and phase error according to the roll-off factor of baseband filter, the output back-offs of nonlinear satellite channel, and loop bandwidth.