• Title/Summary/Keyword: phase detector

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Design of a 960MHz CMOS PLL Frequency Synthesizer with Quadrature LC VCO (960MHz Quadrature LC VCO를 이용한 CMOS PLL 주파수 합성기 설계)

  • Kim, Shin-Woong;Kim, Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.61-67
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    • 2009
  • This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

An Integer-N PLL Frequency Synthesizer Design for The 900MHz UHF RFID Application (900MHz UHF대역 RFID 응용을 위한 Integer-N PLL주파수 합성기 설계)

  • Kim, Sin-Woong;Kim, Young-Sik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.4
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    • pp.247-252
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    • 2009
  • This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

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A Study on Adaptive MMSE RAKE Detector for Forward-link CDMA Communication Systems (순방향 링크의 CDMA통신 시스템에 적용 가능한 적응 MMSE 레이크 수신기)

  • 안태기;이병섭
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9A
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    • pp.1265-1275
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    • 1999
  • An adaptive MMSE detector can be used to cancel the MAI in CDMA system. But standard adaptive MMSE detector cannot be used in real mobile environment due to fast fading channel. Furthermore multipath reception make it more difficult to converge to optimum weight values. In this paper we discuss and model the multipath fading environment in Forward-link Synchronous CDMA channels and propose adaptive MMSE RAKE detector structure which can be applied in the mobile station. A proposed adaptive MMSE detector requires estimation of received signal delay and complex channel coefficients such as amplitude and phase variation. These burden can be solved by utilizing the common pilot channel. The pilot channel may have higher power than the traffic channel, which give more exact channel estimation. Moreover RAKE structure gives more accurate and stable result which can be used as reliable reference signal in multipath fading channel environment. With this structure, conventional adaptive algorithm such as LMS or NLMS can be applied in adaptive MMSE detector.

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Instantaneous Switching-Angle Control Scheme for Precise Speed Control of an SRM (SRM의 정밀속도제어를 위한 순시스위칭각 제어방식)

  • 안진우;오석규;황영문
    • Proceedings of the KIPE Conference
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    • 1997.07a
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    • pp.454-459
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    • 1997
  • The good features of a switched reluctance motor(SRM) are appreciated by the appliance manufactures. And it is spread into a commercial and industries market. The few disadvantage of the motor is higher torque ripple and noise. This paper proposes an instantaneous torque control scheme to control a speed precisely. It adapts phase-locked loop (PLL) technique to control speed precisely. In this control scheme, the phase detector signal of the PLL regulates the switching dwell angle flexibly and the loop filter's signal controls adaptively the instantaneous switching voltage. Experimental results show that drive performance is good with low torque ripple.

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Determination of Gypsogenin by HPLC Using 2, 4-Dinitrophenylhydrazine as a Pre-labeling Reagent (HPLC에 의한 Gypsogenin-2,4-DNPH의 정량)

  • 이왕규;유병기;김박광
    • YAKHAK HOEJI
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    • v.31 no.2
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    • pp.112-115
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    • 1987
  • Gypsogenin was derivatized with 2, 4-dinitrophenylhyclrazine prior to analysis with HPLC. Reversed-phase column (Du pont ODS) was used and the mobile phase was acetonitrile and water (60:40). The effluent was detected at 550nm using an U.V. detector and the retention time was approximately 9.2min. The concentration was quantitated by measuring the area and the detection limit was 0.2$\mu\textrm{g}$.

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Power Factor Improvement of Single-Phase Three-level Boost Converter (단상 Three-level boost converter의 역률개선)

  • 서영조
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.384-387
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    • 2000
  • In this paper Power factor correction circuit of single-phase three-level boost converter is proposed. The advantage of the proposed control scheme for three-level boost converter are low blocking voltage of each power device low THD(Total Harmonic Distortion) and high power factor. The control scheme is based on the current comparator capacitor compensator and region detector, In simulations the proposed system is validated.

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Phase Noise Analysis of 2.4 GHz PLL using SPD (SPD를 이용한 2.4 GHz PLL의 위상잡음 분석)

  • Chae, Myeoung-ho;Kim, Jee-heung;Park, Beom-jun;Lee, Kyu-song
    • Journal of the Korea Institute of Military Science and Technology
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    • v.19 no.3
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    • pp.379-386
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    • 2016
  • In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

On-line Measurement of Partial Discharge (활선상의 부분방전 측정 방법)

  • Paek, Kwang-Hyeon;Choi, Yong-Sung;Park, Dae-Hee;Lee, Chang-Soo
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.1936-1938
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    • 2004
  • In this paper, we discussed measurement method of PD (Partial Discharge) of 22.9[kV] cable. Cable rail track laying portable detector that can detect partial discharge of cable connection ashes by on-line done spot way to detect Lemke equipment and high broadcasting CT sensor that use antenna sensor using ICM mounting was explained. Because measurement corona signal is very big, analysis of partial discharge is difficult state, we used connector. It could be attenuated by 2 times. We found out that corona signal which generated on B phase is flowed on A phase and C phase. It could measure that partial discharge of A phase happens actually. We could confirm that partial discharge of about 250 ${\sim}$ 300 [pC] on A phase is dangerous.

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The shape measurement of 3D object by using the method of interference pattern projection. (간섭무늬 투영 방식의 3차원 형상 측정)

  • 이연태;강영준;박낙규;황용선;백성훈
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2002.05a
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    • pp.271-274
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    • 2002
  • The 3-D measurement using interference pattern projection is very attractive because of its high measuring speed and high sensitivity. When a sinusoidal amplitude grating was projected on an object, the surface-height distribution of the object is translated into a phase distribution of the deformed grating image. The patters was generated by a interferometer, and a PZT was used to shift the fringes on the target surface. The phase-acquisition algorithms are so sufficiently simple that high-resolution phase maps using a CCD camera can be generated in a short time. A working system requires a interferometer, a PZT, and a detector array interfaced to a microcomputer. Results of measurements on the diffused test objects are described.

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Image registration using Hough transform and Phase correlation in Wavelet domain

  • Summar, Bhuttichai;Chitsobhuk, Orachat;Kasemsiri, Watjanapong
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2006-2009
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    • 2005
  • This paper presents a method for registering images using phase correlation technique in fourier domain, hough transform and multi-resolution wavelet. To register images, source and input images are transformed to wavelet domain. An angular transition can be obtained by applying hough transform technique followed by phase correlation. Then we apply phase correlation technique to find x-axis and y-axis transition. We apply wavelet transform to reduce processing time and also use its coefficients as edge information instead of canny detector. With multi-resolution property of wavelet transform, registration time can be greatly reduced. After we get all transition parameters, we transform the input images according to these parameters. Then, we compose and blend all images into a new large image with details of all source images. From our experiment, we can find the accurate transition both x-y translation and angular transition with less error.

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