• Tribology and Lubricants
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• v.38 no.6
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• pp.261-266
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• 2022

Notably, laser surface patterning facilitates tribological applications under lubricated sliding contacts. Consequently, a special pattern that can reduce the coefficient of friction under contact is considered necessary for improved machine efficiency. However, inappropriate pattern designs produce higher friction coefficients and cannot reduce friction. In this study, we use cast iron pins as specimens to investigate their friction and wear characteristics. Moreover, we experimentally investigate the correlation between the friction reduction effect and the design of groove crosshatch patterns fabricated with various angles and widths. We conduct a friction test using a pin-on-disc type tribometer under grease lubrication to study the friction reduction effect of the specimens, and we observe that the average coefficient of friction changes with the crosshatch angle and width. The experiment reveals that grooved crosshatch specimens with a crosshatch angle of 135°maximize friction reduction. The coefficient of friction of the groove specimens with a width of 120 ㎛ is lower than that of the specimens with a width of 200?. The friction reduction effect of the width of the groove is attributed to the density of the groove pattern. Thus, grooved crosshatch patterns can be designed to maximize friction reduction, and the friction property of a grooved crosshatch pattern is found to be related to its width and angle.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.54-54
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• 2009

AFM anodic oxidation has the capability of patterning complex nano-patterns under relatively high speeds and low voltage. We report the fabrication using a atomic force microscopy (AFM) of silicon nano-ribbon and nano-field effect transistors (FETs). The fabricated nano-patterns have great potential characteristics in various fields due to their interesting electronic, optical and other profiles. The results shows that oxide width and the separation between the oxide patterns can be optimally controlled. The subsequently fabricated silicon nano-ribbon and nano-FET working devices were controled by various tip-sample bias-voltages and scan speed of AFM anodic oxidation. The results may be applied for highly integration circuits and sensitive optical sensor applications.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.494-496
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• 1996

The purpose of this study is to investigate the effect of process conditions on pore distribution in porous silicon layer prepared by electrochemical reaction. Porous silicon layers formed on p-type silicon wafer show the network structure of fine porse whose diameters are less than 100${\AA}$. In n-type porous silicon, selective growth was found on the pore surface by wet etching process after PR patterning. And numerical method showed high current density on the pore tip. With this result we confirmed that pore formation has two steps. First step is the initial attack on the surface and second step is the directional growth on the pore tip.

• Journal of Information Display
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• v.1 no.1
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• pp.3-8
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• 2000

We have developed a high performance vertical alignment TFT-LCD (Thin Film Transistor Liquid Crystal Display), that shows a high light transmittance, and wide viewing angle characteristics with an unusually high contrast ratio. In order to optimize the electro-optical properties we have studied the effect of cell parameters, multi-domain structure and retardation film compensation. With the optimized cell parameters and process conditions, we have achieved a 24" wide UXGA TFTLCD monitor (16:10 aspect ratio 1920X1200) showing a contrast ratio of over 500:1, panel transmittance near 4.5%, response time near 25 ms, and viewing angle higher than 80 degree in all directions.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.8 s.173
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• pp.159-164
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• 2005

The Hot Embossing Lithography(HEL) as a method fur the fabrication of the nanostructure with polymer is becoming increasingly important because of its simple process, low cost, high replication fidelity and relatively high throughput. In this paper, we carried out experimental studies and numerical simulations in order to understand the viscous flow of the polymer (PMMA) film during the hot embossing process. To grasp the characteristics of the micro patterning rheology by process parameters (embossing temperature, pressure and time), we have carried out various experiments by using the nickel-coated master fabricated by the deep RIE process and the plasma sputtering. During the hot embossing process, we have observed the characteristics of the viscoelastic behavior of polymer. Also, the viscous flow during the hot embossing process has been simulated by the continuum based FDM(Finite Difference Method) analysis considering the micro effect, such as a surface tension and a contact angle.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.3
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• pp.97-103
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• 2006

The development of a heat exchanger production model based on the microlamination technology and it's economic efficiency is addressed. A microchannel production model is proposed for the high-volume production. The microlamination system is made up of lamina patterning, laminae sorting and laminae bonding. A cost estimation model is developed based on the hewn cycle time and capital equipment costs. An economic efficiency analysis is performed to determine the cost drivers under the different market and product scenarios. The result of the economic efficiency analysis indicated that the device size and the production rate have a great effect on the overall manufacturing cost of microlamination devices. And it can be concluded that the microlamination should focus on bonding larger laminae and reducing both cycle time and warpage.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.770-772
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• 2002

A new dry-processing method of organic gate dielectric film in field-effect transistors (FETs) was proposed. The method use vapor deposition polymerization (VDP) that is continuous and low temperature process. It has the advantages of shadow mask patterning and dry processing in flexible low-cost large area applications. Here, 80 nm-thick Al as a gate electrode was evaporated through shadow mask. Gate insulators used two different polyimides. The one material was 4,4'-oxydiphtahlic anhydride (ODPA) and 4,4'-oxydianiline (ODA). Another was 2,2-bis(3,4-dicarboxyphenyl) Hexafluoropropane Dianhydride (6FDA) and 4,4' -oxydianiline (ODA). These were co-deposited by high-vaccum thermal-evapora and cured at 150 $^{\circ}C$ for 1 hour, respectively. Pentacene as a semiconductor and 100 nm-thick Au as a source and drain electrode were evaporated through shadow mask.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.10a
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• pp.182-185
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• 2005

Indentation pattern and line pattern were machined on borosilicate(Pyrex 7740 glass) surface using the combination of mechanical machining by $Nanoi-indenter\circledR$ XP and HF wet etching, and a etch-mask effect of the affected layer of the nano-scratched and indented Pyrex 7740 glass surface was investigated. In this study, effects of indentation and scratch process with etching time on the morphologies of the indented and scratched surfaces after isotropic etching were investigated from an angle of deformation energies.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.543-544
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• 2006

Pentacene thin film transistors fabricated without photolithographic patterning were fabricated on the plastic substrates. Both the organic/inorganic thin films and metallic electrode were patterned by shifting the position of the shadow mask which accompanies the substrate throughout the deposition process. By using an optically transparent zirconium oxide ($ZrO_2$) as a gate insulator and octadecyltrimethoxysilane (OTMS) as an organic molecule for self-assembled monolayer (SAM) to increase the adhesion between the plastic substrate and gate insulator and the mobility with surface treatment, high-performance transistor with field effect mobility $.66\;cm^2$/V s and $I_{on}/I_{off}$>$10^5$ was formed on the plastic substrate. This technique will be applicable to all structure deposited at low temperature and suitable for an easy process for flexible display.