• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.775-780
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• 2004

In this paper, we propose a simple protection scheme for error prone bit positions of turbo codes using the error detection capability of the CRC, which is almost always employed in practical systems. The proposed scheme based on bit flipping with CRC offers flexibility on selecting the level of protection. Also, not having send additional parity bits or discarding useful bit positions, it offers the best error performance for a given level of protection.

• Korean Journal of Cognitive Science
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• v.4 no.2
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• pp.181-200
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• 1994

In the learning phase of multilyer feedforword neural network,there are problems such that local minimum,learning praralysis and slow learning speed when backpropagation algorithm used.To overcome these problems, the genetic algorithm has been used as learing method in the multilayer feedforword neural network instead of backpropagation algorithm.However,because the genetic algorith, does not have any mechanism for fine-tuned local search used in backpropagation method,it takes more time that the genetic algorithm converges to a global optimal solution.In this paper,we suggest a new GA-BP method which provides a fine-tunes local search to the genetic algorithm.GA-BP method uses gradient descent method as one of genetic algorithm's operators such as mutation or crossover.To show the effciency of the developed method,we applied it to the 3-parity bit problem with analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.105-113
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• 2013

RAID systems have been widely used by connecting several disks in parallel structure. to resolve the delay and bottleneck of data I/O. Recently, SSD based RAID systems are emerging since SSDs have better I/O performance than HDD. However, endurance and power consumption problems due to frequent write operation in SSD based RAID system should be resolved. In this paper, we propose a de-duplication method of parity disk in SSD based RAID system with expensive update cost. The proposed method segments chunk of parity data into small pieces and removes duplicate data, therefore, it can reduce wear-leveling and power consumption by decreasing write operation for duplicated parity data. Experimental results show that bit update rate of the proposed method is 16% in total disk, 31% in parity disk less than that of existing method in RAID-6 system using EVENODD erasure code, and the power consumption of the proposed method is 30% less than that of existing method. Besides the proposed method is 12% in total disk, 32% in parity disk less than that of existing method in RAID-5 system, and the power consumption of the proposed method is 36% less than that of existing method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.430-435
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• 2018

In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.721-728
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• 2010

CAMC (constant amplitude multi-code) has a better performance of error correction in iterative decoding than SPCPC (single parity check product code). CAMC benefits from a processing gain since it belongs to a spread spectrum signal. We show that the processing gain enhances the performance of CAMC. Additional correction of bit errors is achieved in the de-spreading of iteratively decoded signal. If the number of errors which survived the iterative decoding is less than or equal to ($\sqrt{N}/2-1$), all of the bit errors are removed after the de-spreading. We also propose a stopping criterion in the iterative decoding, which is based on the histogram of EI (extrinsic information). The initial values of EI are randomly distributed, and then they converge to ($-E_{max}$) or ($+E_{max}$) over the iterations. The strength of the convergence reflects how successfully error correction process is performed. Experimental results show that the proposed method achieves a gain of 0.2 dB in Eb/No.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.4
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• pp.198-204
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• 2024

LDPC, known for its excellent error correction capability, has been adopted as the channel coding technique in the IRIG 106 standard, which is standard for data transmission methods in the aerospace field. Iterative codes such as LDPC require large block sizes and number of iterations in order to improve performance. However, large number of iterations induce computational complexity and power consumption. To solve these problems, this paper presents a parity check-based early stop algorithm that reduces the average number of iterations while maintaining the same performance. BER performance and iteration reduction amounts are compared between early stop algorithm and conventional method that has fixed number of iterations for various coding rate and information bit size defined in the IRIG 106 standard. Through simulation results, we confirmed required iteration numbers are reduced about 50% above without performance loss.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.535-537
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• 2005

디지털 신호 및 전송부호의 오류검출에는 예전부터 패리티 체크가 사용되어 왔다. 그러나 패리티 체크 기법은 구현 및 알고리즘이 단순, 간결한 우수성이 있지만 특정 데이터 비트의 경우 오류 검출이 불가능하다는 문제점을 가지고 있다. 이후 패리티 체크 기법은 해밍 코드 및 채널 오류 정정을 위한 LDPC 코드와 같은 다양한 오류검출 및 정정 알고리즘에 적용되어 발전되어 왔으며, 그 중 LDPC 코드의 bit-flipping 알고리즘에서는 패리티 기법을 반복적으로 적용하는 방식을 택하고 있다. 본 논문에서는 이러한 채널 오류 정정을 위한 LDPC의 bit-flipping 알고리즘을 이차원 코드에 적용하고, 이 때 bit-flipping 알고리즘이 가지고 있는 문제점을 보완할 수 있는 개선된 LDPC 코드를 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.59-64
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• 2004

We propose a new RLL(run length limited) (2,7) PP(parity preserving) code with 4 RMTR(repeated minimum transition run) for optical recording. The proposed code has better characteristics in terms of density ratio, RMTR, DC(direct current) component suppression, BER(bit error rate) and system complexity than (2,1O) code that currently applied in storage systems and (1,7) PP code that highly recommended as the next generation optical recording system. Some characteristics of the code are described with several simulations. And the proposed code's superiorites in performance is illustrated as compared with the other codes.