• Convergence Security Journal
• /
• v.12 no.4
• /
• pp.85-90
• /
• 2012

DES is a 64-bit binary, and each block is divided into units of time are encrypted through an encryption algorithm. The same key as the symmetric algorithm for encryption and decryption algorithms are used. Conversely, when decryption keys, and some differences may apply. The key length of 64 bits are represented by two ten thousand an d two 56-bit is actually being used as the key remaining 8 bits are used as parity check bits. The 64-bit block and 56-bit encryption key that is based on a total of 16 times 16 modifier and spread through the chaos is completed. DES algorithm was chosen on the strength of the password is questionable because the most widely available commercially, but has been used. In addition to the basic DES algorithm adopted in the future in the field by a considerable period are expected to continue to take advantage of the DES algorithm effectively measures are expected to be in the field note.

• The KIPS Transactions:PartC
• /
• v.11C no.1
• /
• pp.109-114
• /
• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.10C
• /
• pp.935-941
• /
• 2007

In this paper, we suggest the power allocation method which enhances the performance in high SNR for LDPC codes. In this method, bit power is unequally allocated proportionally to the difference of the degree distributions of variable and check nodes of Tanner graph between practically used codes and the codes optimized by density evolution. Simulation is performed to the codes in IEEE 802.16e standards, and the results show that the proposed method works well in high SNR.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.49 no.8
• /
• pp.1-11
• /
• 2012

The multi-code spread spectrum communication system, which spreads data bit stream by multiplexing orthogonal codes, can transmit data in high rate. However it needs the high-cost good linear amplifier because of the multi-level output signal. In order to overcome this drawback several systems making the amplitude of output signal constant with Walsh codes have been proposed. Recently constant amplitude pre-coded multi-code spread spectrum systems using extended m-sequence have been proposed. In this paper we consider an extended m-sequence based constant amplitude multi-code spread spectrum system with code set partitioning. By grouping the orthogonal codes into 4 subsets, not only is the computational complexity of the transceiver reduced but BER performance also improves. It has been shown that parity checking on four detected codes at the receiver can correct code detection error and result in BER performance enhancement. In this paper we propose a improved parity check receiver. We carried out computer simulation to verify feasibility of the proposed algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.5C
• /
• pp.423-431
• /
• 2010

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

• Journal of information and communication convergence engineering
• /
• v.1 no.3
• /
• pp.104-108
• /
• 2003

A biologically inspired fuzzy multilayer perceptron is proposed in this paper. The proposed algorithm is established under consideration of biological neuronal structure as well as fuzzy logic operation. We applied this suggested learning algorithm to benchmark problem in neural network such as exclusive OR and 3-bit parity, and to digit image recognition problems. For the comparison between the existing and proposed neural networks, the convergence speed is measured. The result of our simulation indicates that the convergence speed of the proposed learning algorithm is much faster than that of conventional backpropagation algorithm. Furthermore, in the image recognition task, the recognition rate of our learning algorithm is higher than of conventional backpropagation algorithm.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.639-642
• /
• 2005

This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

• ETRI Journal
• /
• v.21 no.2
• /
• pp.9-21
• /
• 1999

In this paper, to enhance the performance of ${\pi}$/4-DQPSK (${\pi}$/4-differential quadrature phase shift keying), the scheme using nonredundant multiple error correction is proposed and investigated. This scheme for the differential detection of ${\pi}$/4-DQPSK uses the signal output which is delayed for more than two time slots as the parity check bit and applies it to nonredundant multiple error correction. The proposed system was used for studying the performance of ${\pi}$/4-DQPSK with Nonredundant Error Correction (NEC) in additive white Gaussian noise (AWGN) and Nakagami fade modeled mobile communication channel, and it was observed that the performance increased as the error correction capability increased.

• ETRI Journal
• /
• v.37 no.1
• /
• pp.54-60
• /
• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1998.06a
• /
• pp.395-398
• /
• 1998

In this paper, a method for the improvement of learning speed and convergence rate was proposed applied it to physiological neural structure with the advantages of artificial neural networks and fuzzy theory to physiological neuron structure, To compare the proposed method with conventional the single layer perception algorithm, we applied these algorithms bit parity problem and pattern recognition containing noise. The simulation result indicated that our learning algorithm reduces the possibility of local minima more than the conventional single layer perception does. Furthermore we show that our learning algorithm guarantees the convergence.