• 대한기계학회논문집A
• /
• 제20권1호
• /
• pp.35-43
• /
• 1996

A computer program for automatic deriving the symbolic equations of motion for robots using the programming language MATHEMATICA has been developed. The program, developed based on the Lagrange formalism, is applicable to the closed chain robots as well as the open chain robots. The closed chains are virtually cut open, and the kinematics and dynamics of the virtual open chain robot are analyzed. The constraints are applied to the virtually cut joints. As a result, the spatial closed chain robot can be considered as a tree structured open chain robot with kinematic constraints. The topology of tree structured open chain robot is described by a FATHER array. The FATHER array of a link indicates the link that is connected in the direction of base link. The constraints are represented by Lagrange multipliers. The parallel robot, DELTA, having three-dimensional closed chains is modeled and simulated to illustrate the approach.

• 대한안전경영과학회지
• /
• 제6권4호
• /
• pp.155-170
• /
• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• Management Science and Financial Engineering
• /
• 제19권1호
• /
• pp.29-36
• /
• 2013

This paper considers common due-date assignment and scheduling on parallel machines. The main decisions are: (a) deter-mining the common due-date; (b) allocating jobs to machines; and (c) sequencing the jobs assigned to each machine. The objective is to minimize the sum of the penalties associated with common due-date assignment, earliness and tardiness. As an extension of the existing studies on the problem, we consider sequence-dependent setup times that depend on the type of job just completed and on the job to be processed. The sequence-dependent setups, commonly found in various manufacturing systems, make the problem much more complicated. To represent the problem more clearly, a mixed integer programming model is suggested, and due to the complexity of the problem, two heuristics, one with individual sequence-dependent setup times and the other with aggregated sequence-dependent setup times, are suggested after analyzing the characteristics of the problem. Computational experiments were done on a number of test instances and the results are reported.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권4호
• /
• pp.391-406
• /
• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• 정보통신설비학회논문지
• /
• 제10권1호
• /
• pp.7-13
• /
• 2011

Matrix multiplication is a fundamental operation of linear algebra and arises in many areas of science and engineering. This paper introduces an efficient parallel matrix multiplication scheme on N ${\times}$ N mesh-connected SIMD array processor, called multiple hierarchical SIMD architecture (HMSA). The architectural characteristic of HMSA is the hierarchically structured control units which consist of a global control unit, N local control units configured diagonally, and $N^2$ processing elements (PEs) arranged in an N ${\times}$ N array. PEs are communicating through local buses connecting four adjacent neighbor PEs in mesh-torus networks and global buses running across the rows and columns called horizontal buses and vertical buses, respectively. This architecture enables HMSA to have the features of diagonally indexed concurrent broadcast and the accessibility to either rows (row control mode) or columns (column control mode) of 2D array PEs alternately. An algorithmic mapping method is used for performance evaluation by mapping matrix multiplication on the proposed architecture. The asymptotic time complexities of them are evaluated and the result shows that paralle matrix multiplication on HMSA can provide significant performance improvement.

• 한국군사과학기술학회지
• /
• 제20권4호
• /
• pp.566-578
• /
• 2017

For optimizing the operation plan when strike packages attack multiple targets, this article suggests a new mathematical model and a parallel hybrid genetic algorithm (PHGA) as a solution methodology. In the model, a package can assault multiple targets on a sortie and permitted the use of mixed munitions for a target. Furthermore, because the survival probability of a package depends on a flight route, it is formulated as a mixed integer programming which is synthesized the models for vehicle routing and weapon-target assignment. The hybrid strategy of the solution method (PHGA) is also implemented by the separation of functions of a GA and an exact solution method using ILOG CPLEX. The GA searches the flight routes of packages, and CPLEX assigns the munitions of a package to the targets on its way. The parallelism enhances the likelihood seeking the optimal solution via the collaboration among the HGAs.

• 한국정보과학회논문지:시스템및이론
• /
• 제28권9호
• /
• pp.424-433
• /
• 2001

메세지 전달 병렬 프로그램은 프로세스 사이의 메세지 경합에 의하여 실행의 비결정성이 발생하여 순차 프로그램에서 널리 사용되는 순환 디버깅 기법을 사용하기 어렵다. 본 논무은 MPI 병렬 프로그램에서 비결정적 실행에 영향을 미치는 메세지 전달 사건을 정의한 후, 기본실행에서의 사건의 발생순서가 다음의 재실행시 똑 같이 유지되도록 병행실행을 순차생행으로 변환하여 결정적 재실행을 보장함으로써 실행시 마다 같은 오류가 재현되도록 한다. 또한 MPI 병렬 프로그램의 디버깅을 보다 쉽게 하기 위하여 임의의 프로세스를 정짓켰을 때, 다른 모든 프로세스는 정지점 이전에 발생한 모든 사건을 반영하는 최초의 상태에 정지하게 하는 인과관계 정지점을 구현한다. 따라서 인과관계 재실행 기법을 이용하여 병렬 프로그램에서도 순차 프로그램 환경에서와 같이 순환 디버깅 기법을 사용할 수 있게 한다.

• 한국콘텐츠학회논문지
• /
• 제16권10호
• /
• pp.608-616
• /
• 2016

Smith-Waterman(SW) 알고리즘은 DNA 시퀀스 분석에서 중요한 연산 중 하나인 지역 정렬을 처리하는 알고리즘이다. SW 알고리즘은 동적 프로그래밍 방법으로 최적의 결과를 도출할 수 있지만 수행시간이 매우 길다는 문제가 있다. 이를 해결하기 위해서 다수의 노드를 이용한 병렬 분산 처리 기반의 SW 알고리즘이 제안되었다. Apache Spark을 기반으로 하는 병렬 분산 DNA 처리 프레임워크인 ADAM에서도 SW 알고리즘을 병렬로 처리하고 있다. 하지만, ADAM의 SW 알고리즘은 Smith-Waterman 이 동적프로그래밍 기법이라는 특성을 고려하지 않고 있어 최대의 성능을 얻지 못하고 있다. 이 논문에서는 ADAM의 병렬 SW 알고리즘을 개선한다. 제안하는 병렬 SW 기법은 두 단계에 걸쳐 실행된다. 첫 번째 단계에서는 지역정렬 대상인 DNA 시퀀스를 다수의 파티션(partition)으로 분할하고 분할된 각 파티션에 대해서 SW 알고리즘을 병렬로 수행한다. 두 번째 단계에서는 파티션 각각에 대해서 독립적으로 SW를 적용함으로써 발생하는 오류를 보완하는 과정을 역시 병렬로 수행한다. 제안하는 병렬 SW 알고리즘은 ADAM을 기반으로 구현하고 기존 ADAM의 SW와 비교를 통해서 성능을 입증한다. 성능 평가 결과 제안하는 병렬 SW 알고리즘이 기존의 SW에 비해서 2배 이상의 좋은 성능을 내는 것을 확인하였다.

• 정보처리학회논문지:소프트웨어 및 데이터공학
• /
• 제5권5호
• /
• pp.231-242
• /
• 2016

빠른 웹 정보의 변화에 잘 대응하기 위해서는, 사실과 지식이 실제로 유효한 시간과 장소들도 함께 표현하고 그들 간의 관계도 추론할 수 있도록 웹 기술의 확장이 필요하다. 본 논문에서는 그동안 소규모 지식 베이스를 이용한 실험실 수준의 정성 시간 추론 연구들에서 벗어나, 웹 스케일의 대규모 지식 베이스를 추론할 수 있는 병렬 정성 시간 추론기인 MRQUTER의 설계와 구현을 소개한다. Hadoop 클러스터 시스템과 MapReduce 병렬 프로그래밍 프레임워크를 이용해 개발된 MRQUTER에서는 정성 시간 추론 과정을 인코딩 및 디코딩 작업, 역 관계 및 동일 관계 추론 작업, 이행 관계 추론 작업, 관계 정제 작업 등 몇 개의 MapReduce 작업으로 나누고, 맵 함수와 리듀스 함수로 구현되는 각각의 단위 추론 작업을 효율화하기 위한 최적화 기술들을 적용하였다. 대규모 벤치마킹 시간 지식 베이스를 이용한 실험을 통해, MRQUTER의 높은 추론 성능과 확장성을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제11권1호
• /
• pp.39-60
• /
• 2017

In the Cloud, for the scheduling of parallel jobs, there are many tasks in a job and those tasks are executed concurrently on different VMs (Visual machines), where each task of the job will be executed synchronously. The goal of scheduling is to reduce the execution time and to keep the fairness between jobs to prevent some jobs from waiting more time than others. We propose a Cloud model which has multiple Clouds, and under this model, jobs are in different lists according to the waiting time of the jobs and every job has different parallelism. At the same time, a new method-ZOMT (the scheduling parallel tasks based on ZERO-ONE scheduling with multiple targets) is proposed to solve the problem of scheduling parallel jobs in the Cloud. Simulations of ZOMT, AFCFS (Adapted First Come First Served), LJFS (Largest Job First Served) and Fair are executed to test the performance of those methods. Metrics about the waiting time, and response time are used to test the performance of ZOMT. The simulation results have shown that ZOMT not only reduces waiting time and response time, but also provides fairness to jobs.