• Title/Summary/Keyword: parallel processing

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Design of Parallel Algorithms for Conventional Matched-Field Processing over Array of DSP Processors (다중 DSP 프로세서 기반의 병렬 수중정합장처리 알고리즘 설계)

  • Kim, Keon-Wook
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.4 s.316
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    • pp.101-108
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    • 2007
  • Parallel processing algorithms, coupled with advanced networking and distributed computing architectures, improve the overall computational performance, dependability, and versatility of a digital signal processing system In this paper, novel parallel algorithms are introduced and investigated for advanced sonar algorithm, conventional matched-field processing (CMFP). Based on a specific domain, each parallel algorithm decomposes the sequential workload in order to obtain scalable parallel speedup. Depending on the processing requirement of the algorithm, the computational performance of the parallel algorithm reveals different characteristics. The high-complexity algorithm, CMFP shows scalable parallel performance on the array of DSP processors. The impact on parallel performance due to workload balancing, communication scheme, algorithm complexity, processor speed, network performance, and testbed configuration is explored.

Performance Study of Satellite Image Processing on Graphics Processors Unit Using CUDA

  • Jeong, In-Kyu;Hong, Min-Gee;Hahn, Kwang-Soo;Choi, Joonsoo;Kim, Choen
    • Korean Journal of Remote Sensing
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    • v.28 no.6
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    • pp.683-691
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    • 2012
  • High resolution satellite images are now widely used for a variety of mapping applications including photogrammetry, GIS data acquisition and visualization. As the spectral and spatial data size of satellite images increases, a greater processing power is needed to process the images. The solution of these problems is parallel systems. Parallel processing techniques have been developed for improving the performance of image processing along with the development of the computational power. However, conventional CPU-based parallel computing is often not good enough for the demand for computational speed to process the images. The GPU is a good candidate to achieve this goal. Recently GPUs are used in the field of highly complex processing including many loop operations such as mathematical transforms, ray tracing. In this study we proposed a technique for parallel processing of high resolution satellite images using GPU. We implemented a spectral radiometric processing algorithm on Landsat-7 ETM+ imagery using CUDA, a parallel computing architecture developed by NVIDIA for GPU. Also performance of the algorithm on GPU and CPU is compared.

An efficient Storage Reclamation Algorithm for RISC Parallel Processing (RISC 병렬 처리를 위한 기억공간의 효율적인 활용 알고리즘)

  • 이철원;임인칠
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.28B no.9
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    • pp.703-711
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    • 1991
  • In this paper, an efficient storage reclamation algorithm for RISC parallel processing in the object orented programming environments is presented. The memory management for the dynamic memory allocation and the frequent memory access in object oriented programming is the main factor that decreases RISC parallel processing performance. The proposed algorithm can be efficiently allocated the memory space of RISCy computer which is required the frequent memory access, so it can be increased RISC parallel processing performance. The proposed algorithm is verified the efficiency by implementing C language on SUN SPARC(4.3 BSD UNIX).

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Implementation of Parallel Processing Based Pedestrian Detection Using a Modified CENTRIST Algorithm (개선된 CENTRIST 알고리즘을 적용한 병렬처리 기반 보행자 인식 구현)

  • Jung, Jun-Mo
    • Journal of IKEEE
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    • v.18 no.3
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    • pp.398-402
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    • 2014
  • In this paper, we propose a parallel processing method of pedestrian detection algorithm based on ROI-CENTRIST. There is a difficulty in the real-time processing of pedestrian detection in the embedded environment, using the conventional pedestrian detection method. This problem can be solved by a parallel processing method of applying the ROI to the conventional algorithm. The proposed parallel processing method of pedestrian detection using ROI-CENTRIST show the result of 5.2 frames per second, which is about 10% improvement over the conventional pedestrian detection method based on CENTRIST.

Analog Parallel Processing-based Viterbi Decoder using Average circuit (Average 출력회로를 이용한 아날로그 병렬처리 기반 비터비 디코더)

  • Kim, Hyung-Jung;Kim, In-Cheol;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.375-377
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    • 2006
  • A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

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A Parallel Processing System for Visual Media Applications (시각매체를 위한 병렬처리 시스템)

  • Lee, Hyung;Pakr, Jong-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.1A
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    • pp.80-88
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    • 2002
  • Visual media(image, graphic, and video) processing poses challenge from several perpectives, specifically from the point of view of real-time implementation and scalability. There have been several approaches to obtain speedups to meet the computing demands in multimedia processing ranging from media processors to special purpose implementations. A variety of parallel processing strategies are adopted in these implementations in order to achieve the required speedups. We have investigated a parallel processing system for improving the processing speed o f visual media related applications. The parallel processing system we proposed is similar to a pipelined memory stystem(MAMS). The multi-access memory system is made up of m memory modules and a memory controller to perform parallel memory access with a variety of combinations of 1${\times}$pq, pq${\times}$1, and p${\times}$q subarray, which improves both cost and complexity of control. Facial recognition, Phong shading, and automatic segmentation of moving object in image sequences are some that have been applied to the parallel processing system and resulted in faithful processing speed. This paper describes the parallel processing systems for the speedup and its utilization to three time-consuming applications.

Novel Parallel Approach for SIFT Algorithm Implementation

  • Le, Tran Su;Lee, Jong-Soo
    • Journal of information and communication convergence engineering
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    • v.11 no.4
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    • pp.298-306
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    • 2013
  • The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

Frequency Hopping Signal Analysis Using High-Speed Parallel Processing (고속 병렬처리 기법을 활용한 주파수 도약 신호 분석)

  • Lee, Kwang-Yong;Yoon, Hyun-Chul;Lee, Hyeon-Hwi
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.2
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    • pp.251-254
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    • 2014
  • In this paper, we studied a technique of extracting a Frequency Hopping(FH) signal for analysis using high-speed parallel processing structure. Unlike fixed frequency signal, FH signal is difficult to detect and analyze because FH systems use many random frequencies instead of a single carrier frequency. To solve this problem we designed a method that analyze FH signal using high-speed parallel processing. In order to apply parallel processing, we use CUDA using GPU and compare single processing with prarallel processing. As a result, using CUDA on a GPU is about 8.53 times faster than single processing.

Estimation of Hydrodynamic Derivatives by Parallel Processing of Second Order Filter

  • Lee, Kurn-Chul;Kim, Jin-Ki;Rhee, Key-Pyo
    • Journal of Hydrospace Technology
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    • v.1 no.1
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    • pp.66-74
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    • 1995
  • Unknown parameters can be determined by system identification techniques. Extended Kalman filter method was introduced as a real time estimator of hydrodynamic derivatives but it has the problem named the coefficient drift. In this study, 2nd order filter estimates hydrodynamic derivatives in Abkowitz model In order to reduce the coefficient drift, parallel processing is used. The measured state and ship trajectory are compared with the estimated values. Parallel processing of 2nd order filter gives very similar results to parallel processing of extended Kalman filter. Parallel processing cannot not remove the coefficient drift perfectly, but it reduces the estimation error.

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Design of the new parallel processing architecture for commercial applications (상용 응용을 위한 병렬처리 구조 설계)

  • 한우종;윤석한;임기욱
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.5
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    • pp.41-51
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    • 1996
  • In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

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