• Journal of Institute of Control, Robotics and Systems
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• v.6 no.6
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• pp.492-499
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• 2000

In this paper, realization techniques of the parallel processing and the parallel network system for image processing are described. The parallel image processing system is constructed by the characterization of image processing and processor. Several problems are solved to achieve effective parallel processing and processor networking with the particular properties of image processing, which are reduction of communication quantity, equalization of load and delay depreciation on communication. A parallel image input device is developed for the flexible networking of parallel image processing. An abnormal region detection algorithm which is the basic function in machine vision is applied to evaluate the constructed parallel image processing system. The performance and effectiveness of the system are confirmed by experiments.

• Proceedings of the KIEE Conference
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• 2001.07e
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• Korean Journal of Child Studies
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• v.20 no.3
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• pp.231-244
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• 1999

This study examined the effects of short and long term playing of video gamer on children's visual parallel processing. All of the 64 fourth grade subjects were above average in IQ. They were classified into high and low video game users. Instruments were a visual parallel processing task consisting of imagery integration items, computers, and the arcade video game, Pac-Man. Subjects were pre-tested with a visual parallel processing task. After one week, the experimental group played video games for 15 minutes, but the control group didn't play. Immediately following this, all children were post-tested by the same task used on the pretest. The data was analyzed by ANCOVA and repeated measures ANOVA. The results showed that relaying short-term video games improved visual parallel processing and that long term experience with video games also affected visual parallel processing. there were no differences between high and low users in visual parallel processing after playing short term video games.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1489-1496
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• 2010

A feed forward differential architecture of analog PRML decoder is investigated to implement on analog parallel processing circuits. The conventional PRML decoder performs the trellis processing with the implementation of single stage in digital and its repeated use. The analog parallel processing-based PRML comes from the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Shortening the trellis processing stages but implementing it with analog parallel circuits, several benefits including higher speed, no memory requirement and no A/D converter requirement are obtained. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback of the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from all the states of the decoding stage, which enables to be decoded without feedback. The circuit of the proposed architecture is simpler than that of the conventional analog parallel processing structure with the similar decoding performance. Characteristics of the feed forward differential architecture are investigated through various simulation studies.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.2
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• pp.55-59
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• 2002

Parallel processing is able to be used effectively on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on parallel computer architectures lies in the beginning stages because no clear cut paths. This paper presents Jacobian modeling method to supply the base being able to treat power flow by newton's method by the computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• Journal of Information Processing Systems
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• v.13 no.3
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• pp.518-532
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• 2017

Due to the rapid growth of the amount of data, research on bigdata processing has been highlighted. For bigdata processing, CUBRID Shard is able to support query processing in parallel way by dividing the database into a number of CUBRID servers. However, CUBRID Shard can answer a user's query only when the query is required to gain accesses to a single CUBRID server, instead of multiple ones. To solve the problem, in this paper we propose a CUBRID based distributed parallel query processing system that can answer a user's query in parallel and distributed manner. Finally, through the performance evaluation, we show that our proposed system provides 2-3 times better performance on query processing time than the existing CUBRID Shard.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.212-224
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• 2000

In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

• International journal of advanced smart convergence
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• v.8 no.4
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• pp.194-199
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• 2019

As the performance of the system increases, more parallelized data is being processed than single processing of data. Today's cpu structure has been developed to leverage multicore, and hence data processing methods are being developed to enable parallel processing. In recent years desktop cpu has increased multicore, data is growing exponentially, and there is also a growing need for data processing as artificial intelligence develops. This neural network of artificial intelligence consists of a matrix, making it advantageous for parallel processing. This paper aims to speed up the processing of the system by using raspberrypi to implement the cluster building and parallel processing system against the backdrop of the foregoing discussion. Raspberrypi is a credit card-sized single computer made by the raspberrypi Foundation in England, developed for education in schools and developing countries. It is cheap and easy to get the information you need because many people use it. Distributed processing systems should be supported by programs that connected multiple computers in parallel and operate on a built-in system. RaspberryPi is connected to switchhub, each connected raspberrypi communicates using the internal network, and internally implements parallel processing using the Message Passing Interface (MPI). Parallel processing programs can be programmed in python and can also use C or Fortran. The system was tested for parallel processing as a result of multiplying the two-dimensional arrangement of 10000 size by 0.1. Tests have shown a reduction in computational time and that parallelism can be reduced to the maximum number of cores in the system. The systems in this paper are manufactured on a Linux-based single computer and are thought to require testing on systems in different environments.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.5
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• pp.488-495
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• 2009

This paper presents a fast feature extraction method for autonomous mobile robots utilizing parallel processing and based on OpenMP, SSE (Streaming SIMD Extension) and CUDA programming. In the first step on CPU version, the algorithms and codes are optimized and then implemented by parallel processing. The parallel algorithms are debugged to maintain the same level of performance and the process for extracting key points and obtaining dominant orientation with respect to key points is parallelized. After extraction, a parallel descriptor via SSE instructions is constructed. And the GPU version also implemented by parallel processing using CUDA based on the SIFT. The GPU-Parallel descriptor achieves an acceleration up to five times compared with the CPU-Parallel descriptor, but it shows the lower performance than CPU version. CPU version also speed-up the four and half times compared with the original SIFT while maintaining robust performance.

• Journal of Information Processing Systems
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• v.12 no.4
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• pp.724-740
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• 2016

The performance issues of screening large database compounds and multiple query compounds in virtual screening highlight a common concern in Chemoinformatics applications. This study investigates these problems by choosing group fusion as a pilot model and presents efficient parallel solutions in parallel platforms, specifically, the multi-core architecture of CPU and many-core architecture of graphical processing unit (GPU). A study of sequential group fusion and a proposed design of parallel CUDA group fusion are presented in this paper. The design involves solving two important stages of group fusion, namely, similarity search and fusion (MAX rule), while addressing embarrassingly parallel and parallel reduction models. The sequential, optimized sequential and parallel OpenMP of group fusion were implemented and evaluated. The outcome of the analysis from these three different design approaches influenced the design of parallel CUDA version in order to optimize and achieve high computation intensity. The proposed parallel CUDA performed better than sequential and parallel OpenMP in terms of both execution time and speedup. The parallel CUDA was 5-10x faster than sequential and parallel OpenMP as both similarity search and fusion MAX stages had been CUDA-optimized.