• Journal of applied mathematics & informatics
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• 제33권1_2호
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• pp.77-87
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• 2015

Parallel lines are often used to increase production rate in many manufacturing systems where the main line splits into several lines in parallel, and after some operations, they merge into a main line again. Queueing networks with finite buffers have been widely used for modeling and analyzing manufacturing systems. This paper provides an approximation technique for multi-server two-stage networks with merge configuration and blocking which will be a building block for analysis of general manufacturing systems with parallel lines and merge configuration. The main idea of the method is to decompose the original system into subsystems that have two service stations with multiple servers, two buffers and external arrivals to the second stage are allowed. The subsystems are modeled by level dependent quasi-birth-and-death (LDQBD) process.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권11호
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• pp.577-582
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• 2004

In this paper, lumped equivalent circuits for a conventional parallel directional coupler are proposed. This equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of parallel-coupled line. By using the derived design formula, we have designed the 3dB and 4.7dB MMIC couplers at the center frequency of 3.4GHz and 5.6GHz respectively. Measurements for the designed MMIC directional couplers show at 4dB and 5.2dB-coupling value at the center frequency of 3.4GHz and 5.6GHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper

• 전자공학회논문지C
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• 제34C권6호
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• pp.44-50
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• 1997

This paper describes the design and test of an on-line non-invasive network performance monitor (hardware portion) for the SPAX parallel computer. The SPAX parallel computer supports up to 256 intel P6 processors with 4 P6 processors constituting a processign node. The nodes are interconnected with a dual two-level crossbar network calle dXcent-net. Since the performance of the SPAX parallel computer is highly dependent on the proper and efficient operation of the network, an on-line non-invasive network performance monitor (with hardware components) has been developed to aid in the monitoring and tunign of the Xcent-net. Successful testing of a prototype node monitor board and PC interface system shows that our monitor design provides a low-cost practical solution to this problem.

• 대한전기학회논문지:전력기술부문A
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• 제52권1호
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• pp.29-35
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• 2003

This paper presents a fault location algorithm when there are parallel circuits in power system networks. In transmission networks, a fault location method using the distribution factor of fault currents is introduced and in distribution networks a method using direct 3-phase circuit analysis is developed, because the distribution networks are unbalanced. The effect of parallel circuits in fault location is studied in this paper. The effect is important for the range of protecting zones of distance relay in transmission networks and fault location in distribution networks. The result of developed fault location algorithm shows high accuracy in the simulation that using the EMTP.

• Journal of Electrical Engineering and Technology
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• 제13권3호
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• 대한기계학회논문집A
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• 제26권5호
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• pp.843-850
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• 2002

This paper presents a simulation method using the transmission line modeling to reduce simulation runtime of hydraulic control systems. This method is based on separating the system components each other using the transmission line elements prior to simulation, which leads to divide the simulated system into several subsystems suitable for an even more efficient integration. It can also handle nonlinearities and discontinuities without flag signal when restarting integration. By applying variable integration timestep to parallel hydraulic circuits via parallel processing, it is shown that simulation run-time can be reduced significantly compared with that of Runge Kutta method.

• 전력전자학회논문지
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• 제18권4호
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• pp.387-396
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• 2013

This paper investigates the droop control of parallel inverters for an islanded mode of microgrid. Frequency and voltage droop control is one of power control and load demand sharing methods. However, although the active power is properly shared, the reactive power sharing is inaccurate with conventional method due to the unequal line impedances and the power coupling of active - reactive power. In order to solve this problem, an improved droop method with virtual inductor concept and a voltage and current controller properly designed have been considered and analyzed through the PSiM simulation. The performance of improved droop method is analyzed in not only low-voltage line but also medium voltage line.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 A
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• pp.282-284
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• 1999

This paper presents an accurate algorithm for fault location of a single phase to earth fault on a two-parallel transmission line using only one-terminal data. It is impossible to calculate the accurate fault distance, because of the unknown fault resistance and fault current at the fault point. The faulted line circuit and the zero-sequence circuit of two-parallel line are used as a fault location model, which the source impedance of the remote end is not involved. The algorithm can eliminate the effect of load flow and the fault resistance in calculating the fault location.

• Journal of Power Electronics
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• 제18권6호
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• pp.1751-1759
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• 2018

This paper presents parallel-connected inverters to achieve accurate proportional power sharing. Due to line impedance mismatch, reactive power cannot be distributed proportionally when using the conventional $P-{\omega}$ and $\mathcal{Q}-E$ droop. In order to realize reactive proportional power sharing, the ratio of the droop coefficients should be inversely proportional to their power-sharing ratios. Meanwhile, the ratio of the line impedance should be inversely proportional to the desired power-sharing ratio, which is very difficult to be met in practice. In order to deal with this issue, a practical control strategy is presented. By measuring the PCC voltage and using the virtual impedance, the output impedance of individual inverters is reconstructed to counteract the line impedance effect. In order to guarantee system stability, a low pass filter is designed to suppress the bandwidth of the line compensation. Finally, the simulation and experimental results are given to verify the effectiveness of the proposed control strategy.

• 산업경영시스템학회지
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• 제23권56호
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• pp.9-18
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• 2000

This paper considers the problem of two-machine, M-parallel flow shop scheduling to minimize makespan, and proposes a series of heuristic algorithms and a branch and bound algorithm. Two processing times of each job at two machines on each line are identical on any line. Since each flow-shop line consists of two machines, Johnson's sequence is optimal for each flow-shop line. Heuristic algorithms are developed in this paper by combining a "list scheduling" method and a "local search with global evaluation" method. Numerical experiments show that the proposed heuristics can efficiently give optimal or near-optimal schedules with high accuracy. with high accuracy.