• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• International Journal of Contents
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• v.11 no.2
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• pp.15-19
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• 2015

In this paper, we propose an efficient document layout analysis algorithm that includes table detection. Typical methods of document layout analysis use the height and gap between words or columns. To correspond to the various styles and sizes of documents, we propose an algorithm that uses the mean value of the distance transform representing thickness and compare with components in the local area. With this algorithm, we combine a table detection algorithm using the same feature as that of the text classifier. Table candidates, separators, and big components are isolated from the image using Connected Component Analysis (CCA) and distance transform. The key idea of text classification is that the characteristics of the text parallel components that have a similar thickness and height. In order to estimate local similarity, we detect a text region using an adaptive searching window size. An improved adaptive run-length smoothing algorithm (ARLSA) was proposed to create the proper boundary of a text zone and non-text zone. Results from experiments on the ICDAR2009 page segmentation competition test set and our dataset demonstrate the superiority of our dataset through f-measure comparison with other algorithms.

• Korean Journal of Agricultural Science
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• v.27 no.1
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• pp.48-53
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• 2000

The various errors existing in a weight measurement system in most automatic egg sorting system available in Korean poultry farms have caused a large amount of economic losses to the egg producers. The object of this study was an importance of egg measurement system by changing both the number and the arrangements of load cells to reduce measuring errors. The results obtained were summarized as follow : 1. Four arrangements of load cells were selected as follows : layout I : Conventional one load cell method layout II : One load cell located as egg moving direction layout III : Two load cells located facing each other layout IV : Two load cells located as parallel with egg moving direction 2. The results of egg weight measurement according to four arrangements (Layout I, II, III, IV) showed that the average errors were 1.1218g, 0.5953g, 0.7786g, 0.2793g respectively. This indicated that the Layout IV (measuring by 2 load cells located parallel with the egg moving direction) caused the lowest average error and the best in precision. 3. The average vibration of axis X, y, Z were resulted as $5.1937{\times}10^{-3}G$, $9.3604{\times}10^{-3}G$, and $16.8657{\times}10^{-3}G$ respectively when sorting large sized egg. This indicated that the vibration of axis-Z was relatively higher than those of axis-X, and axis-Y.

• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Korea Society for Simulation
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• v.19 no.2
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• pp.107-118
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• 2010

Automotive manufacturing is a complex task that requires the production and assembly of thousands of different components or parts. The engine and the transmission are the major components that constitute a power train system. Although manufacturing processes of an engine are similar, the layouts of the manufacturing lines are different from factory to factory. It is due to the different design concept that how to combine the serial and parallel structures. In this paper, three engine lines of different factories are introduced, and the simulation technology is used to make the performance analysis for different design concepts.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.8
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• pp.1057-1063
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• 1995

This paper describes an approach for constucting a Rectilinear Steiner Tree (RST) derivable from a Minimum Spanning Tree (MST), using Associative Processor (AP). We propose a fast parallel algorithm using AP's basic algorithms which can be realized by the processing capability of rudimentary logic and the selective matching capability of Content- Addressable Memory (CAM). The main idea behind the proposed algorithm is to maximize the overlaps between the consecutive edges in MST, thus minimizing the cost of a RST. An efficient parallel linear algorithm with O(n) complexity to construct a RST is proposed using an algorithm to find a MST, where n is the number of nodes. A node insertion method is introduced to allow the Z-type layout. The routing process which only depends on the neighbor edges and the no-rerouting strategy both help to speed up finding a RST.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.93-102
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• 1995

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.

• Journal of the Korea Society for Simulation
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• v.18 no.2
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• pp.65-75
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• 2009

The semiconductor manufacturing process normally includes a great number of complex sequential steps those are related with various types of equipment. Such equipments are installed with the mixed patterns of serial or parallel structures while considering a number of engineering or environmental factors at the same time. It is thus extremely difficult to change the layout after installation due to expensive costs and other related factors. Because of these reasons, a new investment or layout change, which is usually caused by the production policy such as product mix or production quantity, must be carefully considered. This case study introduces a simulation conducted in a semiconductor parts production company which produces the Board on Chip (BOC)-type of packaging substrate and has plans to change the facility layout. For this study, we used $QUEST^{(R)}$ for simulation modeling and evaluated various strategies which may cause layout changes. Further, the Analytic Hierarchy Process (AHP) is applied to select the best strategy from several alternatives with multiple decision criteria.

• The Research Journal of the Costume Culture
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• v.18 no.2
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• pp.261-276
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• 2010

The analysis of an art trend in the principle dimension starts by observing the object of work in the perspective of formative composition and recognizing it as a universal system. It can be said that it is consistent with an interpretation method for a form theory of formal history by Heinrich W$\ddot{o}$lfflin, a leading form critic in art criticism. Hence, the purpose of this study was to find out what are the formative principles in Renaissance Classicism as a design principle to be applicable to modern fashion by reviewing the formative characteristics of Renaissance Classicism Architecture with which W$\ddot{o}$lfflin directly dealt. As for the theoretical literature review, I used W$\ddot{o}$lfflin's theoretical framework and looked at the Renaissance Classicism Architecture that he studied and examined the possibility of utilizing his theory as a layout principle and the characteristics. As for analysis of design cases, I applied the aforementioned architecture layout principle to modern fashion and conducted case study analysis to delve into distinctive layout principles found in fashion. The study showed that the Renaissance Classicism Architectural Style is marked by linearity, planarity, closing and multiple unity: linearity was expressed in the observation form in fixed frontal view and an emphasis on a tangible silhouette homeogenous and definite line structures; planarity was achieved in the form of paralleled layers of frontal view element, planarity style, and identical and proportional repetition of various sizes.; closing signified the pursuit of complete and clear regularity, and architecture developed in a constructive phase through organizational inevitability and absolute invariability.; multiple unity was expressed in self-completedness and independent parallel of discrete forms and harmony of emphasized individual elements in a totality. Applying these layout characteristics of the Renaissance Classicism Architectural style and to see their individual expressive features, I found out that in adopting layout principles of the Renaissance Classicism Architecture to modern fashion, it turned out to be an emphasis of individual silhouettes, a flattened space, completed objects, organic harmony among independent parts: the emphasis of individual silhouettes was expressed in individual definitiveness of formative lines of clothes in accordance with body joints and an emphasis on formative lines of clothes; the flattened space was marked by single layer structure, planarity of elements of clothes, and listing arrangement by appropriate proportion.; the completedness of the objects was expressed by the stationary state where overall image is fixed, the construction of homogeneous and complete space, and absolute inevitability of internal layout in proportion; lastly, organic harmony of independent parts was stressed in independent completedness of each detail, and organic harmony of the whole. The expressive features would lead to a unique expression style of linear emphasis, proportion, constructive forms, and two-dimensional arrangement. The meaning of this study is follows: The characteristics of art school of thought are given shape by appling & analysing the architectural layout principles of historical art school of thought to modern fashion in the view point of formal construction dimension. The applied possibility of historical art school of thought as the source of inspiration about the fashion design is extended.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.345-352
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• 2006

The purpose of this paper is to evaluate the efficiency of two yard layout of HSS at container terminal, one is that the container yard blocks are placed horizontally in parallel with berth, the other is that the yard blocks are arranged vertically in perpendicular to the berth. In stevedoring system of container terminal, stacking and transport performance are influenced according to block arrangement type of yard. Therefore, efficient design that can improve stacking and transport performance is required. In this paper, we compared their efficiency of two block arrangement concepts in terms of storage capacity, productivity, facility investments, truck service level.