• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.85-90
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• 2015

In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.5-5
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• 1992

The DEVS(discrete event system specification) formalism describes a discrete event system in a hierarchical, modular form. DEVSIM++ is C++ based general purpose DEVS abstract simulator which can simulate systems to be modeled by the DEVS formalism in a sequential environment. We implement P-DEVSIM++ which is a parallel version of DEVSIM++. In P-DEVSIM++, the external and internal event of models can be processed in parallel. To process in parallel, we introduce a hierarchical distributed simulation technique and some optimistic distributed simulation techniques. But in our algorithm, the rollback of a model is localized itself in contrast to the Time Warp approach. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• Journal of the Korea Society for Simulation
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• v.2 no.1
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• pp.31-44
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• 1993

Zeigler's DEVS(Discrete Event Systems Specification) formalism supports formal specification of discrete event systems in a hierarchical , modular manner. Associated are hierarchical, distributed simulation algorithms, called abstract simulators, which interpret dynamics of DEVS models. This paper deals with performance evaluation of P-DEVSIM ++, a parallel simulation environment which implements the DEVS formalism and associated simulation algorithms in a parallel environment. Performance simulator has been developed and used to experiment models of parallel simulation executions in different conditions. The experimental result shows that simulation time depends on both the number of processors in the parallel system and the communication overheads among such processors.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.64-76
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• 1992

The DEVS(discrete event system specificaition) formalism specifies a discrete event system in a hierarchical, modular form. DEVSIM++ is a C++based general purpose DEVS abstract simulator which can simulate systems modeled by the DEVS formalism in a sequential environment. This paper describes P-DEVSIM++which is a parallel version of DEVSIM++ . In P-DEVSIM++, the external and internal event of DEVS models can by processed in parallel. For such processing, we propose a parallel, distributed optimistic simulation algorithm based on the Time Warp approach. However, the proposed algorithm localizes the rollback of a model within itself, not possible in the standard Time Warp approach. An advantage of such localization is that the simulation time may be reduced. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.5
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• pp.147-152
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• 2015

In general, there are two synchronization methods in parallel event-driven simulation, pessimistic approach and optimistic approach. In this paper, we propose a new approach, sporadic synchronization combining both for prediction-based parallel event-driven logic simulation. We claim this hybrid solution is pretty effective to minimize both checkpoint overhead and restart overhead, which are related problems with frequent false predictions for improving the performance of the prediction-based parallel event-driven logic simulation. The experiment has clearly shown the advantage of the proposed approach.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.57-64
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• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• Journal of the Korea Society for Simulation
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• v.3 no.2
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• pp.15-25
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• 1994

Efficient event evaluation and propagation techniques are proposed to enhance the advancement of simulation clocks of conservative and optimistic logic simulation protocols on parallel processing environments. The first idea of the techniques proposed in this paper is to allow more than one event evaluation per simulation cycle and to pack more than one propagation event in a single message. The second idea is to use advancement windows resulted in good performance in parallelism and execution times.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2544-2552
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• 1997

This paper presents three multiprocess models for parallel protocol implementation, that is, (1)channel communication model, (2)fork-join model, and (3)event polling model. For the specification of parallelism for each model, a parallel programming language, Par. C System, is used. to measure the performance of multiprocess models, we implemented the Internet Protocol Suite(IPS) Internet Protocol (IP) for each model by writing the parallel language on the Transputer. After decomposing the IP functions into two parts, that is, the sending side and the receiving side, the parallelism in both sides is exploited in the form of Multiple Instruction Single Data (MISD). Three models are evaluated and compared on the basis of various run-time overheads, such as an event sending via channels in the parallel channel communication model, process creating in the fork-join model and context switching in the event polling model, at the sending side and the receiving side. The event polling model has lower processing delays as about 77% and 9% in comparison with the channel communication model and the fork-join model at the sending side, respectively. At the receiving side, the fork-join model has lower processing delays as about 55% and 107% in comparison with the channel communication model and the event polling model, respectively.

• Journal of the Korea Society of Computer and Information
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• v.15 no.12
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• pp.1-9
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• 2010

This paper describes parallel event-driven remote IT convergence applications which are a combination of traditional industry and IT Technology including advanced communication. In IT convergence system, events can occur currently from many sensors of devices or users. And IT convergence system must have a parallel processing method. In this paper, the parallel processing method was implemented using a thread and we developed a connection method between a device and a mode of communication which is a wireless communication or a power line communication. In addition to that, we developed object modeling, device, user and event modeling, based on XML (eXtensible Markup Language) using object-oriented modeling method. To efficiently show results in real time, systems provide various graphic user interfaces such as a bar graph, a table, and a combination of the two.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1263-1271
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• 1999

This paper designs the performance analysis layer for the various performance analysis of parallel programs using event expressions are similar to the normal program language to analyze the events which display a dynamic state exchange of a program. The event expressions suggest operations for overloading and functions which are needed in performance analysis, such as a filtering operation, data format translation functions, performance analysis, static functions, and etc. By using the event expressions, the programmer can modify the event trace data to analyze the performance and analyze more easily and variously than the pre-developed tools.