• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.478-481
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• 2000

In this paper, we propose a joint coding system for still images using source coding and powerful error correcting code schemes. Our system comprises an LVQ (lattice vector quantization) source coding for wavelet transformed images and turbo coding for channel coding. The parameters of the image encoder and channel encoder have been optimized for an n-D (dimension) cubic lattice (D$_{n}$, Z$_{n}$), parallel concatenation fur two simple RSC (recursive systematic convolutional code) and an interleaver. For decoding the received image in the case of the AWGN (additive white gaussian noise) channel, we used an iterative joint source-channel decoding algorithm for a SISO (soft-input soft-output) MAP (maximum a posteriori) module. The performance of transmission system has been evaluated in the PSNR, BER and iteration times. A very small degradation of the PSNR and an improvement in BER were compared to a system without joint source-channel decoding at the input of the receiver.ver.

• IEIE Transactions on Smart Processing and Computing
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• 제3권3호
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• pp.142-152
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• 2014

Vehicular Ad-hoc Networks (VANETs) are comprised of wireless mobile nodes characterized by a randomly changing topology, high mobility, availability of geographic position, and fewer power constraints. Orthogonal Frequency Division Multiplexing (OFDM) is a promising candidate for the physical layer of VANET because of the inherent characteristics of the spectral efficiency and robustness to channel impairments. The susceptibility of OFDM to Inter-Carrier Interference (ICI) is a challenging issue. The high mobility of nodes in VANET causes higher Doppler shifts, which results in ICI in the OFDM system. In this paper, a frequency domain com-btype channel estimation was used to cancel out ICI. The channel frequency response at the pilot tones was estimated using a Least Square (LS) estimator. An efficient interpolation technique is required to estimate the channel at the data tones with low interpolation error. This paper proposes a robust interpolation technique to estimate the channel frequency response at the data subcarriers. The channel induced noise tended to degrade the Bit Error Rate (BER) performance of the system. Parallel concatenated Convolutional codes were used for error correction. At the decoding end, different decoding algorithms were considered for the component decoders of the iterative Turbo decoder. A performance and complexity comparison among the various decoding algorithms was also carried out.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.417-421
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• 2005

In the recent digital communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that needs many delays over the reception process. Moreover, turbo code has been known as the robust coding methods with the confidence over the fading channel. International Telecommunication Union(ITU) has recently adopted it as the standardization of the channel coding over the third generation mobile communications(IMT-2000). Therefore, in this paper, we proposed the interleaver that has the better performance than existing block interleaver, and modified turbo decoder that has the parallel concatenated structure using MAP algorithm. In the real-time voice and video service over third generation mobile communications, the performance of the proposed two methods was analyzed and compared with the existing methods by computer simulation in terms of reduced decoding delay using the variable decoding method over AWGN and fading channels for CDMA environments.

• 방송공학회논문지
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• 제18권6호
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• pp.816-822
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• 2013

최신 동영상 압축 표준화 기술인 HEVC(High Efficiency Video Coding)는 ITU-T(VCEG)와 ISO-IEC(MPEG)에서 JCT-VC(Joint Collaborative Team on Video Coding)라는 팀을 이루어 진행했으며 표준화의 막바지에 다다르고 있다. 기존 H.264/AVC에 약 50% 이상의 성능 향상을 가져왔으나, 다양한 압축 기술을 사용함에 따라 부호화 및 복호화의 복잡도가 매우 증가하는 문제가 있다. 제안하는 방법은 CPU 병렬처리와 GPU 가속처리를 통해 HEVC의 복잡도를 줄이고, 이를 UHD(Ultra High Definition) 초고해상도 영상에 적용하는 방법으로 UHD($3840{\times}2144$) 영상에서 15fps 이상 인코딩/디코딩의 속도를 가지며, CPU와 GPU간의 데이터 전송 방법의 발전으로 추가적인 속도 향상이 기대된다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권3호
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• pp.1684-1699
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• 2017

The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(4)
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• pp.41-44
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• 2001

Variable length coding (VLC) has been used in many well known standard video coding algorithms such as MPEG and H.26x. However, VLC can not be processed parallelly because of its sequentiality. This sequentiality is a big barrier for implementing a real-time software video codec since parallel schemes can not be applied. In this paper, we propose a new fast VLD (Variable Length Decoding) method based on the probabilistic distribution of symbols in VLC tables used in MPEG as well as H.263 standard codecs. Even though MPEG suggests the table partitioning method, they do not show theoretically why the number of partitioned tables is two or three. We suggest the method for deciding the number of partitioned tables. Applying our scheme to several well-known MPEG-2 test sequences, we can reduce the computational time up to about 10% without any sacrificing video quality

• 대한전자공학회논문지TC
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• 제47권11호
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• pp.36-42
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• 2010

이 논문은 유클리드 기하학과 Circulant Permutation Matrices에서 병렬 구성을 기반으로 하는 Quasi-cyclic Low-density parity-check (QC-LDPC) 코드의 생성을 위한 하이브리드한 접근방식을 나타낸다. 이 방법으로 생성된 코드는 넓은 둘레(Large Girth)와 저밀도(Low Density)를 가진 규칙적인 코드로 나타내어진다. 시뮬레이션 결과는 이 코드들이 반복 복호(Iterative Decoding)를 통해 좋은 성능을 갖는것과 부호화되지 않은 시스템에서 좋은 코딩 이득을 달성하는 것을 보인다.

• 전자공학회논문지B
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• 제30B권11호
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• 한국정보처리학회논문지
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• 제7권1호
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• pp.306-312
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• 2000

본 논문에서는 소형 RS(Reed-Solomon) 디코우더의 효율적인 하드웨어 아키텍처를 제안하였다. 전체 아키텍쳐는 3단 파이프라인 구조를 택하였으며, 디코우딩 연산시, 에러위치다항식은 BMA(Berlekamp-Massey algortihm)에 의한 fast-iteration 방식으로 구하였으며, 계산의 복잡성이 요구도는 신드롬연산 부분은 ROM 테이블을 이용해서 병렬로 수행하고, 에러위치 다항식을 근을 구하는 부분은 Chein search 알고리즘을 응용한 방법을 ROM을 채택하여 계산하였다. 제안된 디코우더로 3심볼 랜덤에러정정을 수행하며, 시스템클록 25MHz를 사용하여 124Mbps의 디코우딩 데이터율을 가짐을 확인할 수 있었다.

• 전자공학회논문지A
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• 제31A권8호
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• pp.111-121
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• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.