• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.2
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• pp.714-727
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• 2015

The hierarchical structure in networks is widely applied in many practical scenarios especially in some emergency cases. In this paper, we focus on a tree network with and without packet loss where one source sends data to n destinations, through m relay nodes employing random linear network coding (RLNC) over a Galois field in parallel transmission systems. We derive closed-form probability expressions of successful decoding at a destination node and at all destination nodes in this multicast scenario. For the convenience of computing, we also propose an upper bound for the failure probability. We then investigate the impact of the major parameters, i.e., the size of finite fields, the number of internal nodes, the number of sink nodes and the channel failure probability, on the decoding performance with simulation results. In addition, numerical results show that, under a fixed exact decoding probability, the required field size can be minimized. When failure decoding probabilities are given, the operation is simple and its complexity is low in a small finite field.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.421-427
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• 2011

Problems encountered in IEEE 802.11 medium access control (MAC) design are interferences from neighboring or hidden nodes and collision from simultaneous transmissions within the same contention floors. This paper presents the selective decoding schemes in MAC protocol for multiple input multiple output ad-hoc networks. It is able to mitigate interferences by using a developed minimum mean-squared error technique. This interference mitigation combined with the maximum likelihood decoding schemes for the Alamouti coding enables the receiver to decode and differentiate the desired data streams from co-channel data streams. As a result, it allows a pair of simultaneous transmissions to the same or different nodes which yields the network utilization increase. Moreover, the presented three decoding schemes and time line operations are optimally selected corresponding to the transmission demand of neighboring nodes to avoid collision. The selection is determined by the number of request to send (RTS) packets and the type of clear to send packets. Both theoretical channel capacity and simulation results show that the proposed selective decoding scheme MAC protocol outperforms the mitigation interference using multiple antennas and the parallel RTS processing protocols for the cases of (1) single data stream and (2) two independent data streams which are simultaneously transmitted by two independent transmitters.

• ETRI Journal
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• v.36 no.1
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• pp.171-174
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• 2014

In weighted bit-flipping-based algorithms for low-density parity-check (LDPC) codes, due to the existence of overconfident incorrectly received bits, the metric values of the corresponding bits will always be wrong in the decoding process. Since these bits cannot be flipped, decoding failure results. To solve this problem, an improved parallel weighted bit flipping algorithm is proposed. Specifically, a reliability-saturation strategy is adopted to increase the flipping probability of the overconfident incorrectly received bits. Simulation results show that the error floor of LDPC codes is greatly lowered.

• Journal of the Korea Convergence Society
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• v.12 no.11
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• pp.69-80
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• 2021

Neural machine translation using deep neural network has emerged as a mainstream research, and an abundance of investment and studies on model structure and parallel language pair have been actively undertaken for the best performance. However, most recent neural machine translation studies pass along decoding strategy to future work, and have insufficient a variety of experiments and specific analysis on it for generating language to maximize quality in the decoding process. In machine translation, decoding strategies optimize navigation paths in the process of generating translation sentences and performance improvement is possible without model modifications or data expansion. This paper compares and analyzes the significant effects of the decoding strategy from classical greedy decoding to the latest Dynamic Beam Allocation (DBA) in neural machine translation using a sequence to sequence model.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.2
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• pp.59-65
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• 2011

All-optical signal processing is expected to offer advantages in speed and power consumption against over electronics signal processing. It has a potential to solve the bottleneck issues of ultra-high speed communication network nodes. All-optical serial-to-parallel and parallel-to-serial data converters would make it possible to easily process the serial data information of a high-speed optical packet without optical-to-electronic-to-optical data conversion. In this paper, we explain the principle of simple and easily expandable all-optical serial-to-parallel and parallel-to-serial data converters based on Mach-Zehnder interferometers. We experimentally demonstrate these data converters at 10Gbit/s serial data rate. They are useful all-optical devices for the all-optical implementations of label decoding, self-routing, control of variable packets, bit-wise logical operation, and data format conversion.

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.401-404
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• 2017

The 360 VR video has a format of a stereoscopic shape such as an isometric shape or a cubic shape or a cubic shape. Although these formats have different characteristics, they have in common that the resolution is higher than that of a normal 2D video. Therefore, it takes much longer time to perform coding/decoding on 360 VR video than 2D Video, so parallel processing techniques are essential when it comes to coding 360 VR video. HEVC, the state of art 2D video codec, uses Wavefront Parallel Processing (WPP) technology as a standard for parallelization. This technique is optimized for 2D videos and does not show optimal performance when used in 3D videos. Therefore, a suitable method for WPP is required for 3D video. In this paper, we propose WPP coding/decoding method which improves WPP performance on cube map format 3D video. The experiment was applied to the HEVC reference software HM 12.0. The experimental results show that there is no significant loss of PSNR compared with the existing WPP, and the coding complexity of 15% to 20% is further reduced. The proposed method is expected to be included in the future 3D VR video codecs.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.325-334
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• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1143-1149
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• 2006

In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.