• Journal of Internet Computing and Services
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• v.19 no.4
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• pp.1-6
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• 2018

In smart cities, data from various kinds of sensors are collected and processed to provide smart services to the citizens. Noise information services with noise maps using the collected sensor data from various kinds of ubiquitous sensor networks is one of them. This paper presents a research result which generates three dimensional (3D) noise maps in real-time for smart cities. To make a noise map, we have to converge many informal data which include big image data of geographical Information and massive sensor data. Making such a 3D noise map in real-time requires the processing of the stream data from the ubiquitous sensor networks in real-time and the convergence operation in real-time. They are very challenging works. We developed our own methodology for real-time distributed and parallel processing for it and present it in this paper. Further, we developed our own real-time 3D noise map generation system, with the methodology. The system uses open source softwares for it. Here in this paper, we do introduce one of our systems which uses Apache Storm. We did performance evaluation using the developed system. Cloud computing was used for the performance evaluation experiments. It was confirmed that our system was working properly with good performance and the system can produce the 3D noise maps in real-time. The performance evaluation results are given in this paper, as well.

• Annual Conference of KIPS
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• 2002.04a
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• pp.11-14
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• 2002

분산 공간 데이터베이스 시스템에서 자주 수행되는 공간 죠인 질의는 공간 데이터의 특징인 대용량성과 복잡성으로 인하여 공간 연산 수행시 연간을 수행하는 서버의 CPU 및 디스크 I/O상의 과부하를 일으킨다. 본 논문은 이러한 분산 광간 데이터베이스 시스템에서 수행 비용이 많이 드는 원격 사이트간의 공간 죠인 질의를 병렬적이며 연쇄적으로 수행하는 기법을 제안한다. 본 기법은 공간 죠인 연산의 대상이 되는 릴레이션들을 공간 연산의 특성에 따라 순서화하고, 그 중 최하위의 죠인에 참여하는 릴레이션들 중 하나를 이등분 하는 방법으로 공간 죠인 연산을 분리한 추, 질의 수행에 참여하는 두 서버에게 죠인 연산을 분배한다. 각 서버는 분할된 공간 죠인 연산을 동시에 연쇄적으로 저리하고 결과를 병합하여 최종 죠인 결과를 생성한다. 본 기법은 릴레이션을 분할하여 죠인을 수행함으로써 공간 연산에 참여하는 객체의 수를 절반으로 줄이며 R-Tree 등의 공간 인덱스 탐색 횟수와 그 범위를 감소시킨다. 또한 연쇄적인 질의 처리로 죠인의 결과인 임시 릴레이션을 생성하지 않으므로 대용량의 데이터에 대한 복잡한 질의에 대해서도 제한 없이 수행한다.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.959-968
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• 1999

several papers have reported that parallel heuristics or hybrid approaches combining several heuristics can get better results. However, the parallelization and hybridization of any search methods on the single CPU type computer need enormous computation time. that case, we need more elegant combination method. For this purpose, we propose Fast Model of Parallel Heuristics(FMPH). FMPH is based on the island model of parallel genetic algorithms and takes local search to the elite solution obtained form each island(sub group). In this paper we introduce how can we adapt FMPH to the job-shop scheduling problem notorious as the most difficult NP-hard problem and report the excellent results of several famous benchmark problems.

• Electronics and Telecommunications Trends
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• v.33 no.5
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• pp.121-134
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• 2018

The Von Neumann based architecture of the modern computer has dominated the computing industry for the past 50 years, sparking the digital revolution and propelling us into today's information age. Recent research focus and market trends have shown significant effort toward the advancement and application of artificial intelligence technologies. Although artificial intelligence has been studied for decades since the Turing machine was first introduced, the field has recently emerged into the spotlight thanks to remarkable milestones such as AlexNet-CNN and Alpha-Go, whose neural-network based deep learning methods have achieved a ground-breaking performance superior to existing recognition, classification, and decision algorithms. Unprecedented results in a wide variety of applications (drones, autonomous driving, robots, stock markets, computer vision, voice, and so on) have signaled the beginning of a golden age for artificial intelligence after 40 years of relative dormancy. Algorithmic research continues to progress at a breath-taking pace as evidenced by the rate of new neural networks being announced. However, traditional Von Neumann based architectures have proven to be inadequate in terms of computation power, and inherently inefficient in their processing of vastly parallel computations, which is a characteristic of deep neural networks. Consequently, global conglomerates such as Intel, Huawei, and Google, as well as large domestic corporations and fabless companies are developing dedicated semiconductor chips customized for artificial intelligence computations. The AI Processor Research Laboratory at ETRI is focusing on the research and development of super low-power AI processor chips. In this article, we present the current trends in computation platform, parallel processing, AI processor, and super-threaded AI processor research being conducted at ETRI.

• Journal of IKEEE
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• v.16 no.4
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• pp.382-388
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• 2012

An H.264/AVC fast motion estimation methodology is presented in this paper. Advanced SIMD based NEON which is one of the parallel processing methods is supported under the ARM Cortex-A9 dual-core platform. NEON is applied to a full search technique with one of the various motion estimation methods and SAD operation count of each macroblock is reduced to 1/4. Pixel values of the corresponding macroblock are assigned to eight 16-bit NEON registers and Intrinsic function in NEON architecture carried out 128 bits arithmetic operations at the same time. In this way, the exact motion vector with the minimum SAD value among the calculated SAD values can be designated. Experimental results show that performance gets improved 30% above average in accordance with the size of image and macroblock.

• Journal of Information Processing Systems
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• v.4 no.4
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• Annual Conference of KIPS
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• 2023.05a
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• pp.389-391
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• 2023

In the era of Big Data, humanity is facing a huge overflow of information. To overcome such an obstacle, many new cutting-edge technologies are being introduced. The movie recommendation system is also one such technology. To date, many theoretical and practical kinds of research have been conducted. Our research also focuses on the movie recommendation system by implementing methods from Social Network Analysis(SNA) and Parallel Programming. We applied the Girvan-Newman algorithm to detect communities of users, and a future package to perform the parallelization. This approach not only tries to improve the accuracy of the system but also accelerates the execution time. To do our experiment, we used the MovieLense Dataset.

• Annual Conference of KIPS
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• 2007.11a
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• pp.644-647
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• 2007

많은 수의 CPU를 사용해 오랜 시간 계산하는 초대형 연산의 경우, 일부 노드나 통신회선의 장애로 연산 실패를 종종 겪는데, 이를 위해 응용 수준의 무정지 연산 시스템의 구현이 중요하다. 본 논문에서는 비동기 알고리즘을 사용한 이전 시스템의 약점을 보완하여, 동기 알고리즘에도 적용가능한 새로운 응용수준의 무정지 연산 시스템을 제안하고 선형시스템의 해법에 적용하였다.

• Proceedings of the Korean Society for Language and Information Conference
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• 2002.02a
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• pp.147-156
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• 2002

Aligned parallel corpora have proved very useful in many natural language processing tasks, including statistical machine translation and word sense disambiguation. In this paper, we describe an alignment technique for extracting transfer mapping from the parallel corpus. During building our system and data collection, we observe that there are three types of translation approaches can be used. We especially focuses on Traditional Chinese and Simplified Chinese text lexical translation and a method for extracting transfer mappings for machine translation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.3231-3244
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• 2016

As processor design has been transiting from homogeneous multicore processor to heterogeneous multicore processor, traditional Amdahl's law cannot meet the new challenges for asymmetric multicore system. In order to further investigate the impact factors related to the Overhead of Data Preparation (ODP) for Asymmetric multicore systems, we evaluate an asymmetric multicore system built with CPU-GPU by measuring the overheads of memory transfer, computing kernel, cache missing and synchronization. This paper demonstrates that decreasing the overhead of data preparation is a promising approach to improve the whole performance of heterogeneous system.