• Proceedings of the KIEE Conference
• /
• 1992.07a
• /
• pp.397-400
• /
• 1992

Many dynamic control have been proposed; however, most of them are limited within stage of simulation study. The main reason is that the computations required for inverse dynamics are far beyond the ability of the present commercially available microprocessors. In this paper, In order to achieve real-time processing in robot dynamic control, a parallel processing computer for robot dynamic control is implemented using two transputer. Two transputer compute two degree of freedom robot. The transputer is a special purpose MPU for parallel processing. Transputers are used in networks to build a high performance concurrent system. A network of transputers and peripheral controllers is constructed using point-to-point communication. To gain most benifit from the transputer architecture, the whole system is programmed in OCCAM which is a high level language for concurrent applications. This control algorithm is applied to the RHINO SCARA type manipulator. We could taked about 438.6 microseconds to compute robot dynamic with two-processors.

• Journal of IKEEE
• /
• v.16 no.4
• /
• pp.304-309
• /
• 2012

As resolution for displays is recently more and more increasing, the amount of data abd calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism[1] used by conventional interpolation, which is to make it easier for parallel processing by rasterizer. This paper implemented designed rasterizer under FPGA environment, and compared it with conventional rasterizer and verified it. This rasterizer is proved to have approximately 50% higher performance compared to conventional one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.820-822
• /
• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.89-96
• /
• 2013

The graphic processor unit (GPU) has been developed to process not only graphic data but also general system data. It shows a better performance than CPU in algorithm for 3D graphics and parallel program. In order to execute algorithm for CPU on GPU, we should understand about GPU architectures and rewrite program considering parallel processing capability and new memory model of GPU. For this reasons, a performance prediction model for the algorithm and its predicted performance through GPU system are required. These can predict problems in GPU application development or construct a performance evaluation standard for GPU. In this paper, we applied the AES encryption algorithms on our performance model and accomplished performance prediction with high accuracy under a heavy workload.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.141-149
• /
• 2013

This paper presents a high-speed intrusion detection process for multi-core video surveillance systems. The high-speed intrusion detection was designed to a parallel process. Based on the analysis of the conventional process, a parallel intrusion detection process was proposed so as to be accelerated by utilizing multiple processing cores in contemporary computing systems. The proposed process performs the intrusion detection in a per-frame parallel manner, considering the data dependency between frames. The proposed process was validated by implementing a multi-threaded intrusion detection program. For the system having eight processing cores, the detection speed of the proposed program is higher than that of the conventional one by up to 353.76% in terms of the frame rate.

• Proceedings of the Korea Water Resources Association Conference
• /
• 2004.05b
• /
• pp.77-89
• /
• 2004

A computer model is developed to assess optimal ground water pumping rates and optimal locations of wells in a coastal region. A sharp interface model is used to simulate the freshwater and salt water flows. Drawdown, upconing, saltwater intrusion and the contamination of well are considered in this model. A genetic algorithm with parallel processing is used to identify the optimal solution.

• Annual Conference of KIPS
• /
• 2013.05a
• /
• pp.476-477
• /
• 2013

Gadget-2 is a scientific simulation code has been used for many different types of simulations like, Colliding Galaxies, Cluster Formation and the popular Millennium Simulation. The code is parallelized with Message Passing Interface (MPI) and is written in C language. There is also a Java adaptation of the original code written using MPJ Express called Java Gadget. Java Gadget writes a lot of checkpoint data which may or may not use the HDF-5 file format. Since, HDF-5 is MPI-IO compliant, we can use our MPJ-IO library to perform parallel reading and writing of the checkpoint files and improve I/O performance. Additionally, to add reliability to the code execution, we propose the usage of Hadoop Distributed File System (HDFS) for writing the intermediate (checkpoint files) and final data (output files). The current code writes and reads the input, output and checkpoint files sequentially which can easily become bottleneck for large scale simulations. In this paper, we propose Sim-Hadoop, a framework to leverage HDFS and MPJ-IO for improving the I/O performance of Java Gadget code.

• Annual Conference of KIPS
• /
• 2009.04a
• /
• pp.1144-1147
• /
• 2009

멀티미디어의 방송 서비스 제공하기 위해서 IP 멀티캐스트의 대안으로써 현재의 인터넷 환경에서도 동시 접속자 수의 제한과 자원 낭비 문제를 효과적으로 해결할 수 있는 다양한 오버레이 멀티캐스트 기법이 제시되고 있다. 본 논문에서는 멀티미디어의 방송 서비스 제공을 위한 병렬 미디어 스트리밍 서버(PMSS : Parallel Media Streaming Server)시스템에 대해 알아보고 오버레이 멀티캐스트 트리 구성 방안으로 분산형 Tree-First 기반의 Spanning tree 구조의 하나인 TBCP기법에 대해 설명하고, TBCP기법의 한계점을 극복하기 위한 오버레이 멀티캐스트 기반의 알고리즘 적용한 효율적이고 향상된 성능을 제공하는 miniOverlay Broadcasting Control Protocol (mOBCP)에 대해 알아본다. 또 제안한 mOBCP 멀티캐스트 기법을 기반으로 PMSS를 이용하여 오버레이 방송 서비스를 제공하는 방안에 제시한다. 성능 비교는 Single 서버와 PMSS로 멀티미디어 방송 서비스를 제공했을 때의 지연시간(Latency)를 비교해 보고 mOBCP기법과 TBCP기법을 PMSS 시스템에서 적용하여 사용자 요구량에 따른 서비스 받는대 걸리는 지연시간을 비교함으로써 제안된 기법의 효율성을 보여주고 있다.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.6
• /
• pp.48-56
• /
• 2010

Recently, we need to dramatically speed up real-time video encoding and decoding on mobile devices because complexity of video CODEC is significantly increasing along with the demand for multimedia service of high-quality and high-definition videos by users. A variety of research is conducted for parallelism of video processing using newly developed multi-core platforms. In this paper, we propose a method of parallelism based on slice partition of video compression CODEC. We propose a novel concept of a parallel slice for parallelism and propose a new coding order to be adequate to the parallel slice which keeps high coding efficiency. To minimize synchronization time of multiple parallel slices, we also propose a synchronization method to determinate whether the parallel slice could be independently decoded or not. Experimental results shows that we achieved 27.5% (40.7%) speed-up by parallelism with bit-rate increase of 3.4% (2.7%) for CIF sequences (720p sequences) by implementing the proposed algorithm on the H.264/AVC.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.8
• /
• pp.2050-2059
• /
• 1999

Multiprocessor scheduling problem has been an important research area for the past decades. The problem is defined as finding an optimal schedule which minimizes the parallel execution time of an application on a target multiprocessor system. Duplication Based Scheduling (DBS) is a relatively new approach for solving multiprocessor scheduling problems. This paper classifies DBS algorithms into two categories according to the task duplication method used. The paper then presents a new DBS algorithm that extracts the strong features of the two categories of DBS algorithms. The simulation study shows that the proposed algorithm achieves considerable performance improvement over existing DBS algorithms with similar time complexity.