• Journal of KIISE
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• v.43 no.5
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• pp.524-530
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• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.

• Journal of IKEEE
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• v.23 no.1
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• pp.80-90
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• 2019

Even though Non-Volatile Memory (NVM) is used for data storage, a page table should be built to access data in it. And this observation leads us to the Persistent Page Table (PPT) scheme that keeps the page table in NVM persistently. By the way, processors have different page table structures and really operational page table cannot be built without virtual and physical addresses of NVM. However, those addresses are determined dynamically when NVM storage is attached to the system. Thus, the PPT should have system-independent and also address-independent structure and really working system-dependent page table should be built from the PPT. Moreover, entries of PPT should be updated atomically and, in this paper, we describe the design of PPT that meets those requirements. And we investigate how file systems can decrease the journaling overhead with the swap operation, which is a new operation created by the PPT. We modified the Ext4 file system in Linux and experiments conducted with Filebench workloads show that the swap operation enhances file system performance up to 60%.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Journal of the Korea Society of Computer and Information
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• v.26 no.2
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• pp.11-18
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• 2021

The flash translation layer(FTL) of SSD maps the logical page number requested from the host to the actual recorded flash memory page number. It is very important to reduce the amount of RAM used to manage the mapping information. In the existing demand-based FTLs, two-level method is applied in which mapping information is also recorded in flash memory pages and only their addresses are managed as a table in RAM. As the capacities of SSDs are growing to tens of terabytes, the amount of RAM for mapping table becomes too large. In this paper, ML-FTL was proposed as a method of managing mapping information in three levels to reduce the amount of RAM required drastically. From an evaluation, the increase in overhead was minimal compared to the conventional two-level method by properly utilizing cache.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.142-150
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• 2021

Open-channel SSD is a new type of Solid-State Disk (SSD) that improves the garbage collection overhead and write amplification due to physical constraints of NAND flash memory by exposing the internal structure of the SSD to the host. However, the host-level Flash Translation Layer (FTL) provided for open-channel SSDs in the current Linux kernel consumes host memory excessively because it use page-level mapping table to translate logical address to physical address. Therefore, in this paper, we implemente a selective mapping table loading scheme that loads only a currently required part of the mapping table to the mapping table cache from SSD instead of entire mapping table. In addition, to increase the hit ratio of the mapping table cache, filesystem information and mapping table access history are utilized for cache replacement policy. The proposed scheme is implemented in the host-level FTL of the Linux kernel and evaluated using open-channel SSD emulator. According to the evaluation results, we can achieve 80% of I/O performance using the only 32% of memory usage compared to the previous host-level FTL.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.63-72
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• 2007

This paper introduces a load-balancing algorithm focusing on distributing web requests evenly into the web cluster servers. The load-balancing algorithms based on conventional periodic load-information update mechanism are not suitable for dynamic page applications, which are common in Cyber Foraging services, due to the problems caused by periodic synchronized load-information updating and the difficulties of work load estimation caused by embedded executing scripts of dynamic pages. Update-on-Finish algorithm solves this problem by using non-periodic load-update mechanism, and the web switch knows the servers' real load information only after their reporting and then distributes new loads according to the new load-information table, however it results in much communication overhead. Our proposed mechanism improve update-on-finish algorithm by using K-Percents-Finish mechanism and thus largely reduce the communication overhead. Furthermore, we consider the different capabilities of servers with a threshold Ti value and propose a load-balancing algorithm for servers with various capabilities. Simulation results show that the proposed K-Percents-Finish Reporting mechanism can at least reduce 50% communication overhead than update-on-finish approach while sustaining better load balancing performance than periodic mechanisms in related work.