• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.238-241
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• 2002

With the popularity of utilization of the Internet among people, the amount of data in the network rapidly increased. So that, the fall of response time from WWW server, which is caused by the network traffic and the burden on m server, has become more of an issue. This problem is encouraged the rearch by redundancy of requesting the same pages by many people, even though they browse the same the ones. To reduce these redundancy, WWW cache server is used commonly in order to store m page data and reuse them. However, the technical uses of WWW cache that different from CPU and Disk cache, is known for its difficulty of improving the cache hit rate. Consecuently, it is difficult to choose effective WWW data to be stored from all data flowing through the WWW cache server. On the other hand, there are room for improvement in commonly used cache replacement algorithms by WWW cache server. In our study, we try to realize a WWW cache server that stresses on the improvement of the stresses of response time. To this end, we propose the new cache replacement algorithm by focusing on the utilizable information of network distance from the WWW cache server to WWW server that possessing the page data of the user requesting.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1669-1679
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• 1996

In this paper, we address the problem of how to replace huffers in multimedia database systems with time-varying skewed data access. The access pattern in the multimedia database system to support audio-on-demand and video-on-demand services is generally skewed with a few popular objects. In addition the access pattem of the skewed objects has a time-varying property. In such situations, our analysis indicates that conventional LRU(least Recently Used) and LFU(Least Frequently Used) schemes for buffer replacement algorithm(ABRN:Adaptive Buffer Replacement using Neural suited. We propose a new buffer replacement algorithm(ABRN:Adaptive Buffer Replacement using Neural Networks)using a neural network for multimedia database systems with time-varying skewed data access. The major role of our neural network classifies multimedia objects into two classes:a hot set frequently accessed with great popularity and a cold set randomly accessed with low populsrity. For the classification, the inter-arrival time values of sample objects are employed to train the neural network.Our algorithm partitions buffers into two regions to combine the best roperties of LRU and LFU.One region, which contains the 핫셋 objects, is managed by LFU replacement and the other region , which contains the cold set objects , is managed by LRUreplacement.We performed simulation experiments in an actual environment with time-varying skewed data accsee to compare our algorithm to LRU, LFU, and LRU-k which is a variation of LRU. Simulation resuults indicate that our proposed algorthm provides better performance as compared to the other algorithms. Good performance of the neural network-based replacement scheme means that this new approach can be also suited as an alternative to the existing page replacement and prefetching algorithms in virtual memory systems.

• Journal of KIISE:Databases
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• v.27 no.1
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• pp.1-12
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• 2000

Many object oriented database systems manage object buffers to provide fast access to objects. Traditional buffer replacement algorithms based on fixed length pages simply assume that the cost incurred by operating a buffer is propertional to the number of buffer faults. However, this assumption no longer holds in an objects buffer where objects are of variable length and the cost of replacing an object varies for each object. In this paper, we propose a cost based replacement algorithm for object buffers. The proposed algorithm replaces the have minimum costs per unit time and unit space. The cost model extends the previous page based one to include the replacement costs and the sizes of objects. The performance tests show that proposed algorithm is almost always superior to the LRU-2 algorithm and in some cases is more than twice as fast. The idea of cost based replacement can be applied to any buffer management architectures that adopt earlier algorithms. It is especially useful in object oriented database systems where there is significant variation in replacement costs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.143-148
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• 2017

Flash Memory which is light and strong external shock as storage of small electronics like smartphone, digital camera, car black box has been widely used. Since the operation speed of the read operation and the write operation are different from each other, and the flash memory has the feature that it is not possible to overwrite, the delete operation is added to solve these problems. Wear-leveling must also be considered, since the number of erase times of the flash memory is limited. Many studies have been conducted on the substitutional algorithms of flash memory based on these characteristics of recent flash memories. So, to solve the problem that has existing buffer replacement algorithm this thesis divide page into 6 groups and when proposed algorithm select victim page, it consider reference page frequency and page recency.

• Journal of KIISE
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• v.42 no.8
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• pp.947-953
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• 2015

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.

• Journal of Korea Multimedia Society
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• v.10 no.5
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• pp.583-593
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• 2007

We study the page replacement algorithms for demand paging, called CFLRU/C, CFLRU/E and DL-CFLRU/E, that reduce the number of erase operations and improve the wear-leveling degree of flash memory. Under the CFLRU/C and CFLRU/E algorithms, the victim page is the least recently used dean page within the pre-specified window. However, when there is not any dean page within the window, the CFLRU/C evicts the dirty page with the lowest frequency while the CFLRU/E evicts the dirty page with the highest number of erase operations. The DL-CFLRU/E algorithm maintains two page lists called the dean page list and the dirty page list, and first finds the page within the dean page list when it selects a victim. However, when it can not find any dean page within the dean page list, it evicts the dirty page with the highest number of erase operations within the window of the dirty page list. In this thesis, we show through simulation that the proposed schemes reduce the number of erase operations and improve the wear-leveling than the existing schemes like LRU.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.469-480
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• 2008

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. To reduce the number of disk accesses, each node caches database pages in its memory buffer. Since a particular page may be cached simultaneously in different nodes, cache consistency should be maintained to ensure that nodes can always access the most recent version of database pages. Most cache consistency schemes proposed in the SD cluster adopted LRU as a buffer replacement algorithm. In this paper, we first present four buffer replacement algorithms that consider the characteristics of the SD cluster. Then we compare the performance of the buffer replacement algorithms. We perform the experiments on a variety of cluster configurations and database workloads. The experiment results show that the proposed algorithms achieve performance improvement up to 5 times of LRU algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.55-57
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• 2002

Linux는 페이지 기반의 가상 메모리 시스템이다. 따라서 메모리가 부족할 때에는 페이지 대치 알고리즘(page replacement algorithm)에 의해 선택된 페이지가 하드디스크로 대치되게 된다. 실시간 시스템에서 이와 같은 페이지 대치가 발생하면 실시간 제약조건을 만족하지 못할 가능성이 크므로 실시간 시스템에서는 이에 맞는 대치 알고리즘이 개발되어야 한다. 본 논문에서는 연성 실시간 시스템에 적합한 N-Chance 기법을 이용한 새로운 페이지 대치 알고리즘을 제안하고 성능을 평가하였다. 새로운 페이지 대치 알고리즘은 기존의 Linux에서 사용하는 second chance 알고리즘을 수정한 것이다. 기존의 알고리즘은 페이지를 대치함에 있어서 사용되지 않는 페이지에 2번의 기회를 준 후 하드디스크로 쫓아내는 방법인데 반하여 본 논문에서 제안하는 방법은 페이지를 사용하는 프로세스가 실시간 프로세스인지 아닌지에 따라서 기회를 주는 횟수를 달리하는 방법이다. N-chance 알고리즘을 사용했을 경우 실시간 제약 조건을 비교적 충족시키면서도 무조건적인 lock으로 인한 메모리 사용의 부담을 줄일 수 있다.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.21-29
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• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.