• Journal of IKEEE
• /
• v.19 no.3
• /
• pp.424-430
• /
• 2015

This paper proposes an optical cryptography application to 2-D page-oriented data based on CFB(Cipher Feedback) mode algorithm. The proposed method uses a free-space optical interconnected dual-encoding technique which performs XOR logic operations in order to implement 2-D page-oriented data encryption. The proposed method provides more enhanced cryptosystem with greater security strength than the conventional CFB block mode with 1-D encryption key due to the huge encryption key with 2-D arrayed page type. To verify the proposed method, encryption and decryption of 2-D page data and error analysis are carried out by computer simulations. The results show that the proposed CFB optical encryption system makes it possible to implement stronger cryptosystem with massive data processing and long encryption key compared to 1-D block method.

• Current Optics and Photonics
• /
• v.5 no.2
• /
• pp.155-163
• /
• 2021

We propose a novel optical encryption scheme for cipher-feedback-block (CFB) mode, capable of encrypting two-dimensional (2D) page data with the use of two-step phase-shifting digital interferometry utilizing orthogonal polarization, in which the CFB algorithm is modified into an optical method to enhance security. The encryption is performed in the Fourier domain to record interferograms on charge-coupled devices (CCD)s with 256 quantized gray levels. A page of plaintext is encrypted into digital interferograms of ciphertexts, which are transmitted over a digital information network and then can be decrypted by digital computation according to the given CFB algorithm. The encryption key used in the decryption procedure and the plaintext are reconstructed by dual phase-shifting interferometry, providing high security in the cryptosystem. Also, each plaintext is sequentially encrypted using different encryption keys. The random-phase mask attached to the plaintext provides resistance against possible attacks. The feasibility and reliability of the proposed CFB method are verified and analyzed with numerical simulations.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.12 no.3
• /
• pp.121-130
• /
• 2017

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.341-344
• /
• 1999

본 논문에서는 DSP 기능을 내장한 32비트 RISC 마이크로프로세서를 위한 버스 제어기를 설계하였다. 연구의 초점은 버스 타이밍, 주소 멀티플렉싱, 리프레쉬, 버스 중재 등을 제어하는 버스제어기를 온칩화 하여 CPU로 하여금 외부 램과 추가적인 장치없이 직접 연결될 수 있도록 한 것이다. 버스 제어기가 관리하는 메모리의 종류는 SRAM, ROM, DRAM, EDO DRAM이며 고속 모드(Fast page mode, EDO page mode 및 RAS-down mode)기능을 지원하며 다양한 Wait를 넣을 수 있다. 주소 영역은 4가지(EMAO-EMA3)이며 내부적으로 7개 의 레지스터가 있고 이들을 이용하여 서로 연결된 세 개의 상태 머신으로 모든 램과의 타이밍을 제어함으로써 공유블록을 활용할 수 있었다. Verilog HDL의 기술하고 Synopsys로 합성한 후 타이밍 검증을 수행한 결과 최악조건에서 53.1㎒로 동작할 수 있었다. 그 후 0.6㎛ single poly triple metal process 공정으로 레이아웃 되었고 면적은 44㎜ × 1.21㎜ 이다.

• Journal of Power Electronics
• /
• v.14 no.5
• /
• pp.1069-1078
• /
• 2014

This study presents the design and implementation of a web-based remote laboratory for a multi-mode single-leg power converter, which is a topic in advanced power electronics course. The proposed laboratory includes an experimental test rig with a multi-mode single-leg power converter and its driver circuits, a measurement board, a control platform, and a LabVIEW-based user interface program that is operated in the server computer. Given that the proposed web-based remote laboratory is based on client/server architecture, the experimental test rig can be controlled by a client computer with Internet connection and a standard web browser. Although the multi-mode single-leg power converter can work at four different modes (main boost, buck-boost, boost-boost, and battery boost modes), only the buck-boost mode is used in the experiment because of page limit. Users can choose the control structure, control parameters, and reference values, as well as obtain graphical results from the user interface software. Consequently, the feedbacks received from students who conducted remote laboratory studies indicate that the proposed laboratory is a useful tool for both remote and traditional education.

• Journal of Korean Institute of Industrial Engineers
• /
• v.41 no.2
• /
• pp.137-143
• /
• 2015

This thesis focuses on the 3D interface tab page type and mode of screen that affect the usability of the small screen devices such as smartphone. The experiments examined eight 3D UI designs, combinations of two modes (Portrait, Landscape) of screen, and four types (Vertical data mountain, Horizontal data mountain, Vertical carousel, Horizontal carousel). Twenty-six participants participated in the experiment. The completion time, preference and fun score were measured. The results showed that the vertical data mountain type provide the best performance in terms of the all conditions. The results of this study suggest a practical approach for the 3D UI tab page design for the small screen devices.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.4
• /
• pp.232-243
• /
• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.

• Korean Journal of Weed Science
• /
• v.10 no.3
• /
• pp.233-239
• /
• 1990

The effect of alachlor treatment on peroxidase synthesis in oat root tips was studied. Alachlor caused increase in the amount of soluble peroxidase in oat root tips, peroxidase activity increase as the rate of alachlor application increased, Alachlor treatment of oats with $1{\times}10^{-6}M$, peroxidase activity increased 0.20 unit higher than that of nontreatment. After 12hr, 65mM of peroxide treatment of oats inhibited 16% root growth, and 130 mM peroxide treatment caused 59% inhibition. With PAGE of peroxidase extracted from normal root tips, PAGE give 4 species($P_2$, $P_3$, $P_4$, and $P_5$ band) of peroxidase. Alachlor significantly activated isoperoxidase. Three isoperoxidase($P_1$, $P_6$, and $P_7$) are synthesized at a increased concentration of alachlor, SDS-PAGE analysis of proteins extracted from oat root tips showed that they were made up of subunits blow 100 kD polypeptide.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.2
• /
• pp.176-183
• /
• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.12
• /
• pp.67-75
• /
• 1999

In this paper, we present an ASIC(Application Specific Integrated Circuit) design of wavelet transform filter Wavelet transform is used in lots of application fields which include image compression, because it has an excellent energy compaction. The operation characteristic and performance of wavelet transform filter are analyzed by using verilog-HDL(Hardware Description Language). In this paper, the designed wavelet transform filter uses line memory to improve data processing rate. Generally, when it reads and writes data of DRAM by using Fast Page Mode, input and output processing is very fast in horizontal direction but substantially slow in vertical direction. The use of line memory solves this low speed processing problem. As a result, though the size of the chip is getting larger, processing time for an image frame becomes 4.66ms. Generally, since the limit of 1 frame processing time on the data of TV video is 33ms, so it is appropriate for TV video.