• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.20 no.3
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• pp.97-102
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• 2014

It was mathematically analyzed at which steps to activate TTI in the cold chain for Alaska pollack, assuming that the performance of a commercial TTI product, and Fresh-check, could not always be optimized for the pollack. Three places were selected for the TTI activation, such as on fishing ship, Busan cooperative fish market, and mart. First, the kinetic and Arrhenius temperature dependent models were experimentally built under isothermal conditions. The color index of TTI and the level of Pseudomonas spp. of pollack were measured at time intervals. Second, the resultant models were used in the mathematical calculations for dynamic temperature conditions included in the cold chain. As a result, the TTI activated at the mart place showed the best agreement between the spoilage time of the pollack and the time for the TTI color to reach its end-point. It was therefore found that it is practically important to optimally select the TTI activation place or time when using a commercial TTI product.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.7-15
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• 2006

In-situ observation of electromigration in thin film pattern of 63Sn-37Pb solder was performed using a scanning electron microscope system. The 63Sn-37Pb solder had the incubation stage of electromigration for edge movement when the current density of $6.0{\times}10^{4}A/cm^2$ was applied the temperature between $90^{\circ}C\;and\;110^{\circ}C$. The major diffusion elements due to electromigration were Pb and Sn at temperatures of $90-110^{\circ}C\;and\;25-50^{\circ}C$, respectively, while no major diffusion of any element due to electromigration was detected when the test temperature was $70^{\circ}C$. The reason was that both the elements of Sn and Pb were migrated simultaneously under such a stress condition. The existence of the incubation stage was observed due to Pb migration before Sn migration at $90-110^{\circ}C$. Electromigration behavior of 63Sn-37Pb solder had an incubation time in common for edge drift and void nucleation, which seemed to be related the lifetime of flip chip solder bump. Diffusivity with $Z^*$(effective charges number) of Pb and Sn were strongly affect the electromigration-induced major diffusion element in SnPb solder by temperature, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.51-55
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• 2006

The green emitting high performance OLEDs using the $Alq_3$-C545T fluorescent system have been fabricated and characterized. In the device fabrication, 2-TNATA [4,4',4'-tris(2-naphthylphenyl-phenylamino)-triphenylamine] as a hole injection material and NPB [N,N'-bis(1-naphthyl)-N,N'-diphenyl-1,1'-biphenyl-4,4'-diamine] as a hole transport material were deposited on the ITO(indium thin oxide)/glass substrate by vacuum evaporation. And then, green color emission layer was deposited using $Alq_3$ as a host material and C-545T[10-(2-benzothiazolyl)-1,1,7,7- tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-[1]/benzopyrano[6,7,8-ij]-quinolizin-11-one] as a dopant. Finally, small molecule OLEDs with structure of ITO/2-TNATA/NPB/$Alq_3$:C545T/$Alq_3$/LiF/Al were obtained by in-situ deposition of $Alq_3$, LiF and Al as the electron transport material, electron injection material and cathode, respectively. Green OLEDs fabricated in our experiments showed the color coordinate of CIE(0.29, 0.65) and the maximum power efficiency of 7.3 lm/W at 12 V with the peak emission wavelength of 521 nm.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.1-6
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• 2008

Thermoelectric properties of calcium cobalt layer structure oxide system, $Ca_3Co_2O_6$ and $Ca_3Co_4O_9$ were investigated at the temperature range of 300 to 1000K for the application of thermoelectric generation. In the composition, the Ca site was partially substituted with Bi, Sr, La, K and the Co site was partially substituted with Mn, Fe, Ni, Cu, Zn. The thermoelectric properties of Bi substituted $Ca_3Co_4O_9$. $Ca_{2.7}Bi_{0.3}Co_4O_9$ for electrical conductivity, Seebeck coefficient and power factor were $85.4({\Omega}$cm)^{-l}, $176.2{\mu}V/K$ and $265.2{\mu}W/K^m$, respectively. The unit thermoelectric couple was fabricated with the p-type of $Ca_{2.7}Bi_{0.3}Co_4O_9$ and n-type ($Zn_{0.98}Al_{0.02}$)O thermoelectrics whose figure-of-merit(Z) were $0.87{\times}10^{-4}/K$ and $0.41{\times}10^4/K$, respectively. The generated thermoelectric power was about 30mV at the temperature difference of 120K in the unit thermoelectric couple.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.79-84
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• 2014

To investigate the plating properties of a diethylene glycol-based Ag immersion plating solution containing citric acid, silver immersion plating was performed in a range from room temperature to $50^{\circ}C$ using sputtered Cu specimens. The used Cu specimens possessed surface structure with large numbers of pinholes which were created with over-acid etching. The Ag immersion plating performed at $40^{\circ}C$ exhibited that the pinholes and copper surface were completely filled with Ag just after 5 min mainly due to galvanic displacement reaction, indicating the best plating properties. Subsequently, the surface morphology of Ag-coated Cu became rougher as the plating time increased to 30 min because of the deposition of silver nanoparticles created by chemical reduction in the solution. The specimen that its overall surface was covered with silver indicated the start of oxidation at temperature higher than around $50^{\circ}C$ in air as compared with pure Cu, indicating enhanced anti-oxidation properties.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.13-17
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• 2003

In this study, new LTCC materials of $ZnWO_4$-LiF system were developed for the application to RF Module fabrication. Pure $ZnWO_4$ must be sintered above $1050^{\circ}C$ in order to obtain up to 98% of full density. The measured dielectric constant ($\epsilon_r$)quality factor ($Q{\times}f0$), and temperature coefficient of resonant frequency ($\tau_f$ were 15.5, 74000 GHz, and $-70ppm^{\circ}C$, respectively. LiF addition resulted in a liquid phase formation at 81$0^{\circ}C$ due to interaction between ZnWO$_4$ and LiF. Therefore, ZnWO$_4$ with 0.5∼1.5 wt% LiF could be densified at $850^{\circ}C$. In the given LiF addition range, the sintering shrinkage increased with increasing LiF content. Addition of LiF slightly lowered the dielectric constant from 15.5 to 14.2∼15 due to lower dielectric constant of LiF. Qxfo value decreased with increasing LiF content. This can be explained in terms of the interaction between LiF and $ZnWO_4$, and inhomogeneity of grain structure.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.47-51
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• 2006

Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A conditioning disk is used during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In this study, we characterized diamond disk with 9 kinds of sample.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.1-6
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• 2007

In this study, the pentacene thin films were prepared by the soluble process, and characterized fur the application of the organic thin film transistor(OTFT) device. To dissolve the pentacene material, two kinds of solvents such as toluene and chloroform were used, and the effects of these solvents on the properties of pentacene thin films coated on ITO/Glass substrate were investigated. Pentacene thin films were prepared by using spin-coating methode and characterized the surface morphology, crystalline and electrical properties. From the AFM measurement, the surface morphology of the pentacene film dissolved with chloroform was improved compared with the one dissolved with toluene solvent. XRD measurement showed that all prepared pentacene film samples were amorphous crystal phases without crystallization of the films. The electrical properties of the pentacene film dissolved with chloroform showed better results than the ones using toluene solvent by hall measurement system. The carrier concentration and the mobility values of pentacene films using chloroform solvent were found to be $-3.225{\times}10^{14}\;cm^{-3}$ and $3.5{\times}10^{-1}\;cm^2{\cdot}V^{-1}{\cdot}S^[-1}$, respectively. The resistivity was about $2.5{\times}10^2\;{\Omega}{\cdot}cm$.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.7-13
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• 2007

In the optical module for optical communications, the flip chip bonding is used fer the precise alignment of the optical fiber and optical device. In flip chip bonding, the optical device is aligned and welded while observing the alignment mark of substrate and chip by using flip chip bonder in order to bond the optical device at the exact position. In this research, optical passive alignment method of photodiode(PD) flip chip bonding is suggested for low cost optical subassembly. By using the visible He-Ne laser (633nm wavelength), photodiode is easily aligned with emitting spot on the optical fiber with the help of stereoscopic alignment system. We compensated wavelength dependent deviation about 4m to find out real alignment position of 1550nm input laser by ray tracing. The maximum optical coupling efficiency between the optical fiber and photodiode was about 23.3%.