• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.331-338
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• 2005

The rapid advances in high power light sources and arrays as encountered in incandescent lamps have induced dramatic increases in die heat flux and power consumption at all levels of high power LED packaging. The lifetime of such devices and device arrays is determined by their temperature and thermal transients controlled by the powering and cooling, because they are usually operated under rough environmental conditions. The reliability of packaged electronics strongly depends on the die attach quality, because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED package have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED package. From the structure function oi the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding presented the thermal resistance of about 3.5K/W. It was much better than those of Ag paste and solder paste presented the thermal resistance of about 11.5${\~}$14.2K/W and 4.4${\~}$4.6K/W, respectively.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.200-206
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• 2019

In this paper, the characteristics of receiving voltage sensitivity about acoustic package in towed array sonar is analyzed through the numerical simulation and design of experiments. Simulation results show that the variation of receiving voltage sensitivity is caused by the structural resonance mode shape on baseline acoustic package. The effect of design parameters of the acoustic package are analyzed through the design of experiments to reduce the deviation of receiving voltage sensitivity. A change of hydrophone shield can thickness (t) is the greatest effect on the deviation of receiving voltage sensitivity. As a result of water tank test, the acoustic package derived from the design of experiments has reduced deviation of receiving voltage sensitivity.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• Proceedings of the SAREK Conference
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• 2009.06a
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• pp.1209-1214
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• 2009

Various automatic temperature control systems have been used widely in Korea for the conservation of heating energy and the enhancement of thermal comfort in residential buildings. But the heating control performance for automatic temperature control systems extensively vary with the design and operational conditions of the heating system, the climate condition and others. It was introduced in this study a numerical calculation program package to analyze heating control characteristics of the automatic temperature control system. This package is able to analyze the room air temperature, return water temperature, supplied heating flux and flow rate, and so on. One the other hand, the simulation results were verified by comparing with the field test results.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1972-1975
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• 2002

In this paper, we have proposed low temperature co-fired ceramic (LTCC) based packaging for RF MEMS devices. The packaging structure is designed and evaluated with 3D full field simulation. 50 ${\Omega}$ matched coplanar waveguide(CPW) transmission line is employed as the test vehicle to evaluate the performances of the proposed package structure. The line is encapsulated with the LTCC packaging lid and connected to the via feed line. To reduce the insertion loss due to the packaging lid, the cavity with via post is formed in the packaging lid. The performances of the package structure is simulated with the different cavity depth and via-to-via length. Simulation results show that the proposed package structure has reflection loss better than 20 dB and insertion loss lower than 0.1 dB from DC to 30 GHz with the cavity depth and via-to-via length of 300 ${\mu}m$ and 350 ${\mu}m$, respectively. To realize the designed package structure, the cavity patterning is tested using the sandblast of LTCC.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.4 no.2
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• pp.20-28
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• 2008

According to IAEA regulations, a transportation package of radioactive material should perform its intended function of containing the radioactive contents after the drop test, which is one of hypothetical accident conditions. Impact limiters attached to a transport cask absorb the most of impact energy. So, it is appreciated to determine properly the shape, size and material of impact limiters. A material data needed in this determination is a dynamic one. In this study, several materials considered as those of impact limiters were tested by a drop weight facility to acquire dynamic material characteristics data. Impact absorbing volume of the impact limiter was derived mathematically for each drop condition. A size optimization of impact limiter was conducted. The derived impact absorbing volumes were applied as constraints. These volumes should be less than critical volumes generated based on the dynamic material characteristics. The derived procedure to decide the shape of impact limiter can be useful at the preliminary design stage when the transportation package's outline is roughly determined and applied as input value.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.91-95
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• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of Fisheries and Marine Sciences Education
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• v.28 no.2
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• pp.456-464
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• 2016

NCS development for construction of marine terminal structure was carried out through following procedures such as analysis on characteristics, analysis on duty, development of the first draft for standards, validation of industry sites, duty competency standards through expert committee, and utilizing package. The results were as follows. Firstly, duty competency was classified as levels from 3 to 7. Educational training institutions were followed by 22 universities, 21 colleges, 16 graduate schools, and 10 high schools. Secondly, developed standards were consisted of duty and competency unit. The name of duty was construction of marine terminal structure and competency units were consisted of 9 items as survey on economic effect, evaluation of conditions on construction environment, plan for construction of structure, construction of transfer, mooring, and power equipment, and construction, startup test, and maintenance of terminal structure. 33 competency unit elements below 9 competency units were developed. Thirdly, utilizing package was developed into 3 areas of life-long career path, training criteria, and guidelines for exam according to national competency standards for in order to develop development of labor's career and perform personal management such as hiring and promotion in industry sites.