• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.4
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• pp.159-164
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• 2009

We fabricated 40 nm-thick cobalt silicide ($CoSi_2$) as a buffer layer, on p-type Si(100) and Si(111) substrates to investigate the possibility of GaN epitaxial growth on $CoSi_2$/Si substrates. We deposited GaN using a HVPE (hydride vapor phase epitaxy) with two processes of process I ($850^{\circ}C$-12 minutes + $1080^{\circ}C$-30 minutes) and process II ($557^{\circ}C$-5 minutes + $900^{\circ}C$-5 minutes) on $CoSi_2$/Si substrates. An optical microscopy, FE-SEM, AFM, and HR-XRD (high resolution X-ray diffractometer) were employed to determine the GaN epitaxy. In case of process I, it showed no GaN epitaxial growth. However, in process II, it showed that GaN epitaxial growth occurred. Especially, in process II, GaN layer showed selfaligned substrate separation from silicon substrate. Through XRD ${\omega}$-scan of GaN <0002> direction, we confirmed that the combination of cobalt silicide and Si(100) as a buffer and HVPE at low temperature (process II) was helpful for GaN epitaxy growth.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.81-86
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• 2004

A new method to improve the wet etching characteristics is described. The anisotropic wet-etching of (100) Si with megasonic wave has been studied in KOH solution. Etching characteristics of p-type (100) 6 inch Si have been explored with and without megasonic irradiation. It has been observed that megasonic irradiation improves the characteristics of wet etching such as an etch uniformity and surface roughness. The etching uniformity on the whole wafer with and without megasonic irradiation were less than ${\pm}1\%$ and more than $20\%$, respectively. The initial root-mean-square roughness($R_{rms}$) of single crystal silicon is 0.23 nm. It has been reported that the roughnesses with magnetic stirring and ultrasonic agitation were 566 nm and 66 nm, respectively. Comparing with the results, etching with megasonic irradiation achieved the Rrms of 1.7 nm on the surface after the $37{\mu}m$ of etching depth. Wet etching of silicon with megasonic irradiation can maintain nearly the original surface roughness after etching process. The results have verified that the megasonic irradiation is an effective way to improve the etching characteristics such as etch uniformity and surface roughness.

• Korean Journal of Materials Research
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• v.21 no.10
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• pp.573-579
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• 2011

Highly textured Ag, Al and Al:Si back reflectors for flexible n-i-p silicon thin-film solar cells were prepared on 100-${\mu}m$-thick stainless steel substrates by DC magnetron sputtering and the influence of their surface textures on the light-scattering properties were investigated. The surface texture of the metal back reflectors was influenced by the increased grain size and by the bimodal distribution that arose due to the abnormal grain growth at elevated deposition temperatures. This can be explained by the structure zone model (SZM). With an increase in the deposition temperatures from room temperature to $500^{\circ}C$, the surface roughness of the Al:Si films increased from 11 nm to 95 nm, whereas that of the pure Ag films increased from 6 nm to 47 nm at the same deposition temperature. Although Al:Si back reflectors with larger surface feature dimensions than pure Ag can be fabricated at lower deposition temperatures due to the lower melting point and the Si impurity drag effect, they show poor total and diffuse reflectance, resulting from the low reflectivity and reflection loss on the textured surface. For a further improvement of the light-trapping efficiency in solar cells, a new type of back reflector consisting of Ag/Al:Si bilayer is suggested. The surface morphology and reflectance of this reflector are closely dependent on the Al:Si bottom layer and the Ag top layer. The relationship between the surface topography and the light-scattering properties of the bilayer back reflectors is also reported in this paper.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.4
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• pp.366-372
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• 2019

In this paper, we fabricated a capacitive humidity sensor with an IDT(Interdigitated) electrode using commercial polyimide containing fluorine, and its properties were measured and analyzed. First, in order to analyze the composition of commercial polyimide, EDS analysis was performed after patterning process on a silicon wafer. The area of the humidity sensor was $1.56{\times}1.66mm^2$, and the width of the electrode and the gap between the electrodes were $3{\mu}m$ each. The number of electrodes was 166 and the length of the electrode was 1.294mm for the sensitivity of the sensor. The fabricated sensor showed that the sensitivity was 24 fF/%RH, linearity <${\pm}2.5%RH$ and hysteresis <${\pm}4%RH$. As a result of measuring the capacitance value according to the frequency change, the capacitance vlaue decreased with increasing frequency. Capacitance deviations with 10kHz and 100kHz were measured as 0.3pF on average.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.6
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• pp.1095-1100
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• 2021

In this study, ITZO thin films were deposited on glass, sapphire, and PEN substrates by RF magnetron sputtering, and their electrical and optical properties were investigated. The resistivity of the ITZO thin film deposited on the glass and sapphire substrates was 3.08×10-4 and 3.21×10-4 Ω-cm, respectively, showing no significant difference, whereas the resistivity of the ITZO thin film deposited on the PEN substrate was 7.36×10-4 Ω-cm, which was a rather large value. Regardless of the type of substrate, there was no significant difference in the average transmittance of the ITZO thin film. Figure of Merits of the ITZO thin film deposited on the glass substrate obtained using the average transmittance in the absorption region of the amorphous silicon thin film solar cell and the absorption region of the P3HT : PCBM organic active layer were 10.52 and 9.28×10-3 Ω-1, respectively, which showed the best values. Through XRD and AFM measurements, it was confirmed that all ITZO thin films exhibited an amorphous structure and had no defects such as pinholes or cracks, regardless of the substrate type.

• Fire Science and Engineering
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• v.32 no.6
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• pp.108-116
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• 2018

A melted bead microstructure can be divided into a deformed and undeformed layer. Measurement errors occur in the presence of a deformed layer, which should be removed through grinding/polishing whilst preserving the original structure. This paper proposes a grinding/polishing process to analyze the microstructure of copper melted beads. For the removal of the deformed layer, the correlation between the abrasive type/size, the polishing time and polishing rate was analyzed and the thickness of the deformed layer was less than $1{\mu}m$. The results suggest a new grinding/polishing procedure: silicon carbide abrasive $15{\mu}m$ (SiC P1200) 2 min, and $10{\mu}m$ (SiC P2400) 1 min; and diamond abrasive $6{\mu}m$ 8 min, $3{\mu}m$ 6 min, $1{\mu}m$ 10 min, and $0.25{\mu}m$ 8 min. In addition, a method of increasing the sharpness of the microstructure by chemical polishing with $0.04{\mu}m$ colloidal silica for 3 min at the final stage is also proposed. The overall grinding/polishing time is 38 min, which is shorter than that of the conventional procedure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.596-601
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• 2020

Silicon carbide is considered a potentially useful material for high-temperature electronic devices because of its large band gap energy and p-type or n-type conduction that can be controlled by impurity doping. Accordingly, the thermoelectric properties of -SiC powder prepared by refined diatomite were investigated for high value-added applications of natural diatomite. -SiC powder was synthesized by a carbothermal reduction of the SiO₂ in refined diatomite using carbon black. An acid-treatment process was then performed to eliminate the remaining impurities (Fe, Ca, etc.). n-Type semiconductors were fabricated by sintering the pressed powder at 2000℃ for 1~5h in an N2 atmosphere. The electrical conductivity increased with increasing sintering time, which might be due to an increase in carrier concentration and improvement in grain-to-grain connectivity. The carrier compensation effect caused by the remaining acceptor impurities (Al, etc.) in the obtained -SiC had a deleterious influence on the electrical conductivity. The absolute value of the Seebeck coefficient increased with increasing sintering time, which might be due to a decrease in the stacking fault density accompanied by grain or crystallite growth. On the other hand, the power factor, which reflects the thermoelectric conversion efficiency of the present work, was slightly lower than that of the porous SiC semiconductors fabricated by conventional high-purity -SiC powder, it can be stated that the thermoelectric properties could be improved further by precise control of an acid-treatment process.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.39.2-39.2
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• 2010

In this work we have investigated electrical and optical properties of interface for ITO/Si with shallow doped emitter. The ITO is prepared by DC magnetron sputter on p-type monocrystalline silicon substrate. As an experimental result, The transmittance at 640nm spectra is obtained an average transmittance over 85% in the visible range of the optical spectrum. The energy bandgap of ITO at oxygen flow from 0% to 4% obtained between 3.57eV and 3.68eV (ITO : 3.75eV). The energy bandgap of ITO is depending on the thickness, sturcture and doping concentration. Because the bandgap and position of absorption edge for degenerated semiconductor oxide are determined by two competing mechanism; i) bandgap narrowing due to electron-electron and electron-impurity effects on the valance and conduction bands (> 3.38eV), ii) bandgap widening by the Burstein-Moss effect, a blocking of the lowest states of the conduction band by excess electrons( < 4.15eV). The resistivity of ITO layer obtained about $6{\times}10^{-4}{\Omega}cm$ at 4% of oxygen flow. In case of decrease resistivity of ITO, the carrier concentration and carrier mobility of ITO film will be increased. The contact resistance of ITO/Si with shallow doped emitter was measured by the transmission line method(TLM). As an experimental result, the contact resistance was obtained $0.0705{\Omega}cm^2$ at 2% oxygen flow. It is formed ohmic-contact of interface ITO/Si substrate. The emitter series resistance of ITO/Si with shallow doped emitter was obtained $0.1821{\Omega}cm^2$. Therefore, As an PC1D simulation result, the fill factor of EWT solar cell obtained above 80%. The details will be presented in conference.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.258-258
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• 2016

최근 디스플레이 산업의 발전에 따라 고성능 디스플레이가 요구되며, 디스플레이의 백플레인 (backplane) TFT (thin film transistor) 구동속도를 증가시키기 위한 연구가 활발히 진행되고 있다. 트랜지스터의 구동속도를 증가시키기 위해 높은 이동도는 중요한 요소 중 하나이다. 그러나, 기존 백플레인 TFT에 주로 사용된 amorphous silicon (a-Si)은 대면적화가 용이하며 가격이 저렴하지만, 이동도가 낮다는 (< $1cm2/V{\cdot}s$) 단점이 있다. 따라서 전기적 특성이 우수한 산화물 반도체가 기존의 a-Si의 대체 물질로써 각광받고 있다. 산화물 반도체는 비정질 상태임에도 불구하고 a-Si에 비해 이동도 (> $10cm2/V{\cdot}s$)가 높고, 가시광 영역에서 투명하며 저온에서 공정이 가능하다는 장점이 있다. 하지만, 차세대 디스플레이 백플레인에서는 더 높은 이동도 (> $30cm2/V{\cdot}s$)를 가지는 TFT가 요구된다. 따라서, 본 연구에서는 차세대 디스플레이에서 요구되는 높은 이동도를 갖는 TFT를 제작하기 위하여, amorphous In-Ga-Zn-O (a-IGZO) 채널하부에 화학적으로 안정하고 전도성이 뛰어난 SnO2 채널을 얇게 형성하여 TFT를 제작하였다. 표준 RCA 세정을 통하여 p-type Si 기판을 세정한 후, 열산화 공정을 거쳐서 두께 100 nm의 SiO2 게이트 절연막을 형성하였다. 본 연구에서 제안된 적층된 채널을 형성하기 위하여 5 nm 두계의 SnO2 층을 RF 스퍼터를 이용하여 증착하였으며, 순차적으로 a-IGZO 층을 65 nm의 두께로 증착하였다. 그 후, 소스/드레인 영역은 e-beam evaporator를 이용하여 Ti와 Al을 각각 5 nm와 120 nm의 두께로 증착하였다. 후속 열처리는 퍼니스로 N2 분위기에서 $600^{\circ}C$의 온도로 30 분 동안 실시하였다. 제작된 소자에 대하여 TFT의 전달 및 출력 특성을 비교한 결과, SnO2 층을 형성한 TFT에서 더 뛰어난 전달 및 출력 특성을 나타내었으며 이동도는 $8.7cm2/V{\cdot}s$에서 $70cm2/V{\cdot}s$로 크게 향상되는 것을 확인하였다. 결과적으로, 채널층 하부에 SnO2 층을 형성하는 방법은 추후 높은 이동도를 요구하는 디스플레이 백플레인 TFT 제작에 적용이 가능할 것으로 기대된다.