• 대한전자공학회논문지SD
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• 제47권10호
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• pp.14-22
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• 2010

기존의 n-type metal-oxide-semiconductor field effect transistor(NMOSFET)은 $n^+/p^{(+)}/n^+$ type의 이온 주입을 통하여 소스/채널/드레인 영역을 형성하게 된다. 30 nm 이하의 채널 길이를 갖는 초미세 소자를 제작함에 있어서 설계한 유효 채널 길이를 정확하게 얻기 위해서는 주입된 이온들을 완전히 activation하여 전류 수준을 향상시키면서도 diffusion을 최소화하기 위해 낮은 thermal budget을 갖도록 공정을 설계해야 한다. 실제 공정에서의 process margin을 완화할 수 있도록 오히려 p-type 채널을 형성하져 않으면서도 기존의 NMOSFET의 동작을 온전히 구현할 수 있는 junctionless(JL) MOSFET이 연구중이다. 본 논문에서는 3차원 소자 시뮬레이션을 통하여 silicon nanowire(SNW) 구조에 접목시킨 JL MOSFET을 최적 설계하고 그러한 조건의 소자에 대하여 conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) 등의 기본적인 고주파 특성을 분석한다. 채널 길이는 30 nm이며 설계 변수는 채널 도핑 농도와 채널 SNW의 반지름이다. 최적 설계된 JL SNW NMOSFET에 대하여 동작 조건($V_{GS}$ = $V_{DS}$ = 1.0 V)에서 각각 367.5 GHz, 602.5 GHz의 $f_T$, $f_{max}$를 얻을 수 있었다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 춘계학술대회
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• pp.295-298
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• 2007

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• Mass Spectrometry Letters
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• 제12권2호
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• pp.47-52
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• 2021

Evaluating the impurity concentrations in semiconductor thin films using time of flight secondary ion mass spectrometry (ToF-SIMS) is an effective technique. The mass interference between isotopes and matrix element in data interpretation makes the process complex. In this study, we have investigated the doping concentration of phosphorus in, phosphorus doped silicon thin film on glass using ToF-SIMS in the dynamic mode of operation. To overcome the mass interference between phosphorus and silicon isotopes, the quantitative analysis of counts to concentration conversion was done following two routes, standard relative sensitivity factor (RSF) and SIMetric software estimation. Phosphorus doped silicon thin film of 180 nm was grown on glass substrate using hot wire chemical vapor deposition technique for possible applications in optoelectronic devices. Using ToF-SIMS, the phosphorus-31 isotopes were detected in the range of 10¹~10⁴ counts. The silicon isotopes matrix element was measured from p-type silicon wafer from a separate measurement to avoid mass interference. For the both procedures, the phosphorus concentration versus depth profiles were plotted which agree with a percent difference of about 3% at 100 nm depth. The concentration of phosphorus in silicon was determined in the range of 10¹⁹~10²¹ atoms/cm³. The technique will be useful for estimating distributions of various dopants in the silicon thin film grown on glass using ToF-SIMS overcoming the mass interference between isotopes.

• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

• 신재생에너지
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• 제2권2호
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• pp.4-8
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient Reff lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 한국전기전자재료학회논문지
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• 제22권7호
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• pp.616-621
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• 2009

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2006년도 춘계학술대회
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• pp.183-186
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient $R_{eff}$ lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 센서학회지
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• 제17권5호
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• pp.346-349
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• 2008

A metal-semiconductor-metal (MSM) ultraviolet (UV) photodetector (PD) is proposed as an effective UV sensing device for integration with a GaN n-channel MISFET on auto-doped p-type GaN grown on a silicon substrate. Due to the high hole barrier of the metal-p-GaN contact, the dark current density of the fabricated MSM PD was less than $3\;nA/cm^2$ at a bias of up to 5 V. Meanwhile, the UV/visible rejection ratio was 400 and the cutoff wavelength of the spectral responsivity was 365 nm. However, the UV/visible ratio was limited by the sub-bandgap response, which was attributed to defectrelated deep traps in the p-GaN layer of the MSM PD. In conclusion, an MSM PD has a high process compatibility with the n-channel GaN Schottky barrier MISFET fabrication process and epitaxy on a silicon substrate.

• 전자공학회논문지A
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• 제31A권4호
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• pp.70-76
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• 1994

A humidity sensing device based on a new humidity sensing principle is designed and fabricated in this study. The silicon thermopile is consisted of 25 couples of p-type diffused layer/Al strips. The internal resistance and the Seebeck coefficient are 300kl and 537$\mu$V/K, respectively Fabricated sensors showed linear response characteristics proportional to relative humidity changes with a sensitivity of 9$\mu$V/%RH in the range from 20% to 90%.