• Journal of the Optical Society of Korea
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• v.15 no.1
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• pp.1-3
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• 2011

We characterize and analyze silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth of CMOS-APDs based on two types of PN junctions, N-well/P-substrate and $P^+$/N-well junctions, are compared and analyzed. It is demonstrated that the CMOS-APD using the $P^+$/N-well junction has higher responsivity as well as higher photodetection bandwidth than N-well/P-substrate. In addition, the important factors influencing CMOS-APD performance are clarified from this investigation.

• Applied Microscopy
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• v.42 no.3
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• pp.158-163
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• 2012

Detailed comparison of low-voltage scanning electron microscopy and electron holography techniques for two-dimensional (2D) dopant profiling was carried out with using the same multilayered p-n junction specimen. The dopant profiles obtained from two methods are in good agreement with each other. It demonstrates that reliability of dopant profile measurement can be increased through precise comparison of 2D profiles obtained from various microscopic techniques.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.332.2-332.2
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• 2016

Two dimensional transition-metal dichalcogenides (TMDs) semiconductors are attractive materials for optoelectric devices because of their direct energy bandgap and transparency. To investigate the feasibility of transparent p-n junctions, we have fabricated a p-n heterojunction consisting of p-type WSe2 and n-type MoS2 flakes since WSe2 and MoS2 with proper electrode metals exhibit p-type and n-type behaviors, respectively. These heterojunctions exhibits gate-tunable rectifying behaviors and photovoltaic effects (ECE ~ 0.2%) indicating that p-n junctions were formed. In addition, photocurrent and photovoltaic effects were observed under light illumination, which were dependent on the gate voltage. In addition, the photocurrent mapping images indicate that the photovoltaic effects comes from the junction area. Possible origins of gate-tunability are discussed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.349-352
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• 2001

In this paper, novel device structure in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA) for ultra pn junction formation. Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20 nm for arsenic dosage (2$\times$10$^{14}$ $\textrm{cm}^2$), excimer laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.257.2-257.2
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• 2015

In this paper, we report on the 10.33% efficient thin film/bulk tandem solar cells with the top cell made of amorphous silicon thin film and p-type bulk crystalline silicon bottom cell. The tunneling junction layers were used the doped nanocrystalline Si layers. It has to allow an ohmic and low resistive connection. For player and n-layer, crystalline volume fraction is ~86%, ~88% and dark conductivity is $3.28{\times}10-2S/cm$, $3.03{\times}10-1S/cm$, respectively. Optimization of the tunneling junction results in fill factor of 66.16 % and open circuit voltage of 1.39 V. The open circuit voltage was closed to the sum of those of the sub-cells. This tandem structure could enable the effective development of a new concept of high-efficiency and low cost cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.273-273
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• 2010

Recently, extensive research on hetero-junction arrays has been reported owing to its unique band gaps dissimilar to that of homo-junctions. These hetero-junction devices can be used in laser, solar cells, and various sensors. We report on the facile method to fabricate SWCNTs/SnO2 nanowires hetero-junction arrays on flexible polyimide substrate. Each SWCNT field effect transistor (FET) and SnO2 nanowire FET exhibits the purely p- and n-type charactersistics with ohmic contact properties. Such formed pn-junctions showed rectification behaviors reproducibly with a rectification ratio of ${\sim}3{\times}103$ at 1 V and ideality factors about 12. The pn-junctions also showed a good gate modulation behavior.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.964-969
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• 2014

In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• Journal of the Korean Vacuum Society
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• v.21 no.4
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• pp.185-192
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• 2012

p-n junction temperature and thermal resistance of Light Emitting Diode (LED) package are affected by the chip size due to the change of the thermal density and the external quantum efficiency considering the heat dissipation through conduction. In this study, forward voltage was measured for two different size LED chips, 24 mil and 40 mil, which consist constitute 16-chip package. p-n junction temperature and thermal resistance were determined by thermal transient analysis, which were discussed in connection with the electrical characteristics of the LED chip and the structure of the LED package.