• Advances in materials Research
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• v.5 no.1
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• pp.55-66
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• 2016

This paper describes a study on the effects of $Mg_2Si_{(p)}$ addition on the microstructure, porosity, and mechanical properties namely hardness and tensile properties of AA332 composite. Each composite respectively contains 5, 10, 15, and 20 wt% reinforcement particles developed by a stir-casting. The molten composite was stirred at 600 rpm and melted at $900^{\circ}C{\pm}5^{\circ}C$. The $Mg_2Si$ particles were wrapped in an aluminum foil to keep them from burning when melting. The findings revealed that the microstructure of $Mg_2Si_{(p)}/AA332$ consists of ${\alpha}$-Al, binary eutectic ($Al+Mg_2Si$), $Mg_2Si$ particles, and intermetallic compound. The intermetallic compound was identified as Fe-rich and Cu-rich, formed as polygonal or blocky, Chinese script, needle-like, and polyhendrons or "skeleton like". The porosity of $Mg_2Si_{(p)}/AA332$ composite increased from 8-10% and the density decreased from 9-12% from as-cast. Mechanical properties such as hardness increased for over 42% from as-cast and the highest UTS, elongation, and maximum Q.I were achieved in the sample of 10% $Mg_2Si$. The study concludes that combined with AA332, the amount of 10 wt% of$Mg_2Si$ is a suitable reinforcement quantity with the combination ofAA332.

• Resources Recycling
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• v.21 no.5
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• pp.65-71
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• 2012

The equilibrium distribution of bismuth and lead between molten PbO-$SiO_2$ slag and bismuth phase was studied in the temperature range of $775^{\circ}C$ to $850^{\circ}C$ in a MgO crucible. The oxygen partial pressure of atmosphere was controlled by $P_{CO2}/P_{CO}$ ratio. The value of $(%PbO)_{slag}/[%Pb]_{metal}$ increased with increasing $SiO_2$ content of slag, and the value of $(%Bi_2O_3)_{slag}/[%Bi]_{metal}$ decreased with increasing $SiO_2$ content of slag. The concentration of Pb in metal increased with increasing temperature. These experimental results agreed well with the thermodynamic prediction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• Korean Journal of Materials Research
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• v.21 no.6
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• pp.341-346
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• 2011

In this study, we inserted a Zn buffer layer into a AZO/p-type a-si:H layer interface in order to lower the contact resistance of the interface. For the Zn layer, the deposition was conducted at 5 nm, 7 nm and 10 nm using the rf-magnetron sputtering method. The results were compared to that of the AZO film to discuss the possibility of the Zn layer being used as a transparent conductive oxide thin film for application in the silicon heterojunction solar cell. We used the rf-magnetron sputtering method to fabricate Al 2 wt.% of Al-doped ZnO (AZO) film as a transparent conductive oxide (TCO). We analyzed the electro-optical properties of the ZnO as well as the interface properties of the AZO/p-type a-Si:H layer. After inserting a buffer layer into the AZO/p-type a-Si:H layers to enhance the interface properties, we measured the contact resistance of the layers using a CTLM (circular transmission line model) pattern, the depth profile of the layers using AES (auger electron spectroscopy), and the changes in the properties of the AZO thin film through heat treatment. We investigated the effects of the interface properties of the AZO/p-type a-Si:H layer on the characteristics of silicon heterojunction solar cells and the way to improve the interface properties. When depositing AZO thin film on a-Si layer, oxygen atoms are diffused from the AZO thin film towards the a-Si layer. Thus, the characteristics of the solar cells deteriorate due to the created oxide film. While a diffusion of Zn occurs toward the a-Si in the case of AZO used as TCO, the diffusion of In occurs toward a-Si in the case of ITO used as TCO.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.3
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• pp.233-240
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• 2023

p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiO_x structure. It simultaneously achieves surface passivation and enhances the carriers' selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiO_x layer achieves the highest implied open-circuit voltage (iV_oc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiO_x) and poly-silicon layer (poly-Si), as well as the advancement of the SiO_x and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.

• Journal of Digital Convergence
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• v.12 no.7
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• pp.291-296
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• 2014

Inserting a $SiO_2$ layer underneath the p-pad electrode as the current blocking layer (CBL) structure and extending p-metal finger patterns, the GaN LEDs using an indium-tin-oxide (ITO) layer show the improved light output intensity, resulting from better current spreading and reduced light loss on the surface of p-pad metal. The LEDs with an oxide layer of $100{\mu}m$-pad-width and $6{\mu}m$-finger-width have better light output intensities than those with an oxide layer of $105{\mu}m$-pad-width and $12{\mu}m$-finger-width. Using the ATLAS device simulator from Silvaco Corporation, the current density distributions on the active layer in CBL LEDs have been investigated.

• Journal of the Korean Ceramic Society
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• v.48 no.6
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• pp.621-624
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• 2011

In order to deposit a homogeneous and uniform ${\beta}$-SiC films by chemical vapor deposition, we constructed the phase-diagram of ${\beta}$-SiC over graphite and silicon via computational thermodynamic calculation considering pressure(P), temperature(T) and gas composition(C) as variables in $C_3H_8-SiCl_4-H_2$ system. During the calculation, the ratio of Cl/Si and C/Si is maintained to be 4 and 1, respectively, and H/Si ratio is varied from 2.67 to 15,000. The P-T-C diagram showed very steep phase boundary between SiC+C and SiC region perpendicular to H/Si axis and also showed SiC+Si region with very large H/Si value of ~6700. The diagram can be applied not only to the prediction of the deposited phase composition but to compositional variation due to the temperature distribution in the reactor. The P-T-C diagram could provide the better understanding of chemical vapor deposition of silicon carbide.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.3
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• pp.90-94
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• 2004

The variation of electrical properties of (Ba,Sr)$TiO_3$ [BST] thin films for Metal-Insulator-Semiconductor (MIS) capacitors was investigated. BST thin films were deposited on p-Si(100) substrates by the RF magnetron sputtering with temperature range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of AUBST/$SiO_2$/Si sandwich structure were measured for various conditions. We examined the characteristics of MIS capacitor with various oxygen pressure, substrate temperature and (Ba+Sr)/Ti ratio. It was found that the leakage current was reduced in MIS capacitor with high quality $SiO_2$ layer was grown on bare p-Si substrate by thermal oxidation. The BST MIS structure showed relatively high capacitance even though it is the combination of high-dielectric BST thin films and $SiO_2$ layer. The charge state densities of the MIS capacitors and Current-voltage characteristics of the MIS capacitor were investigated. By applying $SiO_2$ layer between BST thin films and Si substrate, low leakage current of $10^{-10}$ order was observed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.8
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• pp.481-485
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• 2015

We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.

• Transactions on Electrical and Electronic Materials
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• v.2 no.2
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• pp.26-31
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• 2001

This paper presents the electrochemical etch-stop characteristics of single-crystal Si(001) wafers in tetramethyl ammonium hydroxide(TMAH):isopropyl alcohol(IPA):pyrazine solutions. The addition of pyrazine to TMAH:IPA solutions increased the etch rate of (100) Si, thus the etching time required by the etch-stop process shortened. The current-voltage(I-V) characteristics of n- and p-type Si in TMAH:IPA:pyrazine solutions were obtained, respectively. Open circuit potential(OCP) and passivation potential(PP) of n- and p-type Si, respectively, were obtained and applied potential was selected between n- and p-type Si PPs. The electrochemical etch-stop method was used to fabricate 801 microdiaphragms of 20 ${\mu}{\textrm}{m}$ thickness on a 5-inch Si wafer. The average thickness of fabricated 801 microdiaphragms on one Si wafer was 20.03 ${\mu}{\textrm}{m}$ and the standard deviation was $\pm$0.26 ${\mu}{\textrm}{m}$. The Si surface of the etch-stopped microdiaphragm was extremely flat with no noticeable taper or nonuniformity.